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THE FAUST AND GOETHE PROGRAMS

IP.com Disclosure Number: IPCOM000006717D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-25
Document File: 4 page(s) / 262K

Publishing Venue

Motorola

Related People

Donald Horr: AUTHOR [+2]

Abstract

Because of the increasing size and complexity of integrated circuits, fault simulation and automatic test generation are among the most computer intensive tasks associated with integrated circuit design. This paper desctii two computer prwgrams which reduce the num- ber of faults that must be simulated or tested and which also assist in reducing the engineering effort involved in analysis of undetected faults.

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MO7VUOLA INC. Technical Developments Volume 17 December 1992

THE FAUST AND GOETHE PROGRAMS

by Donald Horr and John Salick

ally be around six times as many possible stuck faults in a circuit as there are logic gates. To detect a fault, there must be an input sequence for a good part which pro- duces the opposite logic value at the fault site. The two different values must then be propagated to a circuit output so the difference can be observed. The difficuhy of justifying the opposite value at the fault site and then propagating the faulty value to an output becomes exponentially more difIicult as the size of the circuit increases. For large semiconductor designs, the num- bers of faults can run into the millions. In addition, the size and complexity of these designs make fault justift- cation and propagation extremely difficuh. It is there- fore very important to minimize the number of faults which must be simulated or tested.

FAULT COLLAPSE

  If the effect of one fault is distinguishable from that of another fault, the two faults are said to be equivalent. Only one fault out of a set of equivalent faults needs to be tested. For example, the stuck-high fault on the input of an inverter is equivalent to the stuck-low fault on the output of the inverter.

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ABSTRACT

  Because of the increasing size and complexity of integrated circuits, fault simulation and automatic test generation are among the most computer intensive tasks associated with integrated circuit design. This paper desctii two computer prwgrams which reduce the num- ber of faults that must be simulated or tested and which also assist in reducing the engineering effort involved in analysis of undetected faults.

INTRODUCTlON

  The two programs are named fat& (fault stripper) and goerhe. The faurr program enumerates faults and seeks to reduce the numbers of faults which must be simulated or tested. The goethe program analyzes the results of a fault simulation or automatic test generation and tries to determine the detection status of fault which have not been stimulated. The unusual features of these programs at that: 1) they are rule based, 2) they are inde- pendent of the simulator being used, and 3) they use the concept of an ignoredfnulf. (Ignored faults are explained below.)

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ME STUCK FAULT MODEL

   The sfuclcfaulf model is commonly used in the semi- conductor industry to stimulate defects in a manufac- tured part. The model assumes that a defect manifests itself as either a constant high logic level or a constant 10%~ logic level on a gate input or output. The model further assumes that only one defect (and hence one fault) is present at a time. A I& for a fault is a sequence of input vectors which results in at least one output value of a faulty part having a different logic level than a good part would have. Fazdf simulation is a prwess which deter- mines how many stuck faults a set of input vectors can detect.

  Because there are assumed to be two possible faults...