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A SIMPLIFIED REFRACTORY GATE PROCESS FOR HIGH PERFORMANCE GaAs RF FETs

IP.com Disclosure Number: IPCOM000006718D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-25
Document File: 2 page(s) / 115K

Publishing Venue

Motorola

Related People

Vernon R O'Neil: AUTHOR [+5]

Abstract

The Authors have devised an improved process for As one can see above, the critical gate dimension is production of refractory gate GaAs FETs intended for set by the amount of undercut of the gate etch. This can RF applications. This process will make production sim- be diflicult to control to better than 0.1 micron because pler and reduce the variation in RF parameters of the the metal etch tends to be somewhat isotropic. Also, finished devices. In order to show the advantages of this one would like to make contact to the top of the gate process, below we will first describe the present with a low resistance metal layer such as aluminum, ("MAFET") process as used at Motorola then we will and this can require a very tine via opening involving describe the improved ("I&WET II") process and dis- tricky processing because the gate may be 0.5 micron cuss the advantages this new process achieves. or less in width.

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M-LA INC. Technical Developments Volume 17 December 1992

A SIMPLIFIED REFRACTORY GATE PROCESS FOR HIGH PERFORMANCE GaAs RF FETs

by Vernon R O'Neil, George B. Norris, Vijay Nair, Charles E. Weitzel, and Saeid N. Tehrani

INTRODUCTION:

  The Authors have devised an improved process for As one can see above, the critical gate dimension is production of refractory gate GaAs FETs intended for set by the amount of undercut of the gate etch. This can RF applications. This process will make production sim- be diflicult to control to better than 0.1 micron because pler and reduce the variation in RF parameters of the the metal etch tends to be somewhat isotropic. Also, finished devices. In order to show the advantages of this one would like to make contact to the top of the gate process, below we will first describe the present with a low resistance metal layer such as aluminum, ("MAFET") process as used at Motorola then we will and this can require a very tine via opening involving describe the improved ("I&WET II") process and dis- tricky processing because the gate may be 0.5 micron cuss the advantages this new process achieves. or less in width.

THE "MAFET" REFRACTORY GATE GaAs FET PROCESS:

The MAIXT refractory gate GaAs FET process has many attractive features. Among them are:

  * The gate is put in place and shaped before the implants are annealed. The annealing process with the gate already in place provides better Schottky charac- teristics than is possible by simply depositing a gate metal on a previously annealed surface.

  In order to do the highly implanted source drain implants without a masking step, a dielectric capable of blocking the implant is deposited and removed without a mask by RIE etching, leaving a "spacer" at the edge of the gate. This spacer then allows the implant to be kept away from the edge of the gate where it would cause thigh capacitance and low breakdown voltage.

Ion Implant Beam

  * Subsequent processing can be done at tempera- tures higher than that used with gates made from low melting point metals such as aluminum.

  - Selfalignment techniques can be used to allow the source. and drain to be implanted without an additional masking step.

  However, the MAFET refractory gate process shown below also has some complex processing that can corn- plicate manufacturing. The first is related to the forma- tion of the gate structure as shown below:

Underci( Gate layer

  This "spacer" process has the advantage of self alignment without a mask, but it does add another deposition and etch. Furthermore, the spacer is limited to about a 2500 Angstrom offset between...