Browse Prior Art Database

BOUNDARY SCAN FPGA PROGRAMMING AND TESTING

IP.com Disclosure Number: IPCOM000006729D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-28
Document File: 1 page(s) / 65K

Publishing Venue

Motorola

Related People

Bob V. Lazaravich: AUTHOR

Abstract

Field Programmable Logic Array (FPGA) devices are now beginning to rival custom gate arrays in terms of complexity and, to some extent, number of gates. Devices with 2,000 to 10,000 equivalent internal gates are quite common. Just about any new hardware design contains several programmable devices. A basic prob- lem with these devices has always been how to re-program them after they are soldered to a circuit board. The devices themselves are ohen m-programmable; how- ever, sockets are seldom used for reasons of both relia- bility and cost savings. Removing a device from a board tore-program it is generally not practical.

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MO7WROLA INC. Technical Developments Volume 18 March 1993

BOUNDARY SCAN FPGA PROGRAMMING AND TESTING

by Bob V. Lazaravich

   Field Programmable Logic Array (FPGA) devices are now beginning to rival custom gate arrays in terms of complexity and, to some extent, number of gates. Devices with 2,000 to 10,000 equivalent internal gates are quite common. Just about any new hardware design contains several programmable devices. A basic prob- lem with these devices has always been how to re-program them after they are soldered to a circuit board. The devices themselves are ohen m-programmable; how- ever, sockets are seldom used for reasons of both relia- bility and cost savings. Removing a device from a board tore-program it is generally not practical.

  The Boundary Scan interface (IEEE TAP P1149.1) is a five-wire serial interface with a defined protocol that provides a way to test the internal logic of complex devices. The Boundary Scan interface could easily be used to do the initial programming of programmable devices. A serial string, N-bits long, would be shied into the device. The N bit string represents the 'fuse' pattern to program into the device plus any necessary Boundary Scan protocol bits. A separate ProgramKlk pin on the device would be pulsed to initiate the device programming. The N-bit string would be programmed (ii parallel) into the 'fuses' of the FPGA device. Ideally, all fuses would be programmed at the same time. After programming, the 'fuse' data is pa...