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LOW VOLTAGE, LOW AREA DAC TECHNIQUE

IP.com Disclosure Number: IPCOM000006734D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-28
Document File: 3 page(s) / 140K

Publishing Venue

Motorola

Related People

John E. (Ted) Hanna: AUTHOR

Abstract

This report describes a circuit technique for the design of Digital to Analog Converters (DACs) which provides an improved output voltage compliance for pre- cision DACs, typically those with 7-10 bits of resolution. The technique has been used for 7 and 8 bit DACs on a 3GHz bipolar process and produced untrimmed 11 bit linearities at room temperature.

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MO7VROLA INC. Technical Developments Volume ia March 1993

LOW VOLTAGE, LOW AREA DAC TECHNIQUE

by John E. (Ted) Hanna

1.0 SUMMARY 2.0 CIRCUIT

  This report describes a circuit technique for the In the following schematic, a 'I-hit DAC, the four design of Digital to Analog Converters (DACs) which Most Signilicant Bits (MSBs) are generated by fairly clas- provides an improved output voltage compliance for pre- sic area scaling and resistor ratioing techniques, while the cision DACs, typically those with 7-10 bits ofresolution. three Least Sign&ant Bits (LSBs) are generated with the The technique has been used for 7 and 8 bit DACs on a new technique. Note the similarity in structure between 3GHz bipolar process and produced untrimmed 11 bit the MSB's and LSBs, as this technique requires no addi- linearities at room temperature. tional large voltage offsets or current splitting techniques.

FIGURE 1.7.Bit DAC Schematic

2.1 MSB CIRCUIT

  The example DAC has a full scale current just under 800uA, so its MSB is 4OOuA. In the following circuit which shows the four MSBs, note the emitter area scal- ing of the current source transistors, XQ42,27, 41 and 38 indicated by the np (number in parallel) parameter. Also note that the emitter resistors for these current sources are made of identical length parallel resistors.

The resistor for the SOuA source is a single resistor, while the one for the 400uA source has eight segments in parallel. Thus both the transistor and resistor for the MSB take advantage of the improved matching that results statistically from the use of multiple devices. Darlington switches are required to make the base cur- rent errors negligible. The bases of the current sources are fed from a low impedance reference.

0 Motorola. Inc. ,993 15

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MOTOROLA INC. Technical Developments Volume 18 March 1993

FIGURE 2. MSB Circuitry for 7-Bit DAC

2.2 LSB CIRCUIT

  If the emitter area scaling and resistor paralleling were extended for additional bits, the ratios of emitter size and resistor values start becoming very large, resulting in large circuit areas. In the example above, the four bits require an 8:l ratio, and extending the technique to only 7-bits would end up with 128:l ratios. Although various techniques have been developed to avoid this, they have generally required the use of secondary current splitting arrangements which require added voltage to operate.

The following circuit uses an R-2R ladder network
(e.g. XRl and XR17) to devklop high resistor ratios using onl...