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Browse Prior Art Database

SELECTIVE SUBSTRATE CONTACT WITH DUAL WIDTH TRENCHES

IP.com Disclosure Number: IPCOM000006735D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-28
Document File: 4 page(s) / 169K

Publishing Venue

Motorola

Related People

James J. Wang: AUTHOR

Abstract

For high speed bipolar and BiCMOS transistors, parasitic capacitances must be minimized. Base and col- lector side-walls add sign&ant capacitance to substrate. Reducing side-wall capacitances therefore improve tran- sistor speed and performance. In addition, new chip pack- ages require die front side contact to substrate. Trench technology can provide isolation between transistors, cre- ate minimal side-wall capacitances, and allow electrical contact top- substrate from the die front surface.

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MOTOROLA INC. Technical Developments Volume 19 March 1993

SELECTIVE SUBSTRATE CONTACT WITH DUAL WIDTH TRENCHES

by James J. Wang

   For high speed bipolar and BiCMOS transistors, parasitic capacitances must be minimized. Base and col- lector side-walls add sign&ant capacitance to substrate. Reducing side-wall capacitances therefore improve tran- sistor speed and performance. In addition, new chip pack- ages require die front side contact to substrate. Trench technology can provide isolation between transistors, cre- ate minimal side-wall capacitances, and allow electrical contact top- substrate from the die front surface.

  Single width trench isolation and substrate contact process has been developed for MOSAIC V. The MOSAIC V process requires a mask sequence to define isolation trenches, RIE etch trenches, form dielectric liner oxide, fill trenches with polysilicon, and finally planarize the polysilicon till. Then, after junction process sequences, follow with another mask sequence to define the sub- strate contact trenches, then RIE etch stacked films, RIE etch trenches, fdl trenches with doped polysilicon, and again planarize the ffl. These two process sequences result in trenches as shown on Figure 1.

  Dual width trench concept allows process simpliti- cation of two separate trench process sequences to just one trench sequence. Yet, dual width process has both types of trenches as shown on Figure 2c. Process sequences of dual width trench process arc compared with a standard process (attachment 1). Eleven process steps which are no longer required are marked with an
x. Process simpliication results in the elimination of 1 mask layer, eliminate additional/d&licult trench etch and planarization processes, decrease cycle time, and fur- thermore, eliminate electrical junction between doped substrate trench plugs and doped buried collector.

  Selective substrate contact with dual width trenches incorporates both layouts of 3pm width substrate con- tact trenches along with lpm width isolation trenches on the same mask. Both types of trenches arc patterned and etched at the same time. Liner dielectric fti limes side-walls of both types $trenches. During the 8OOOA polysilicon or other material fll process, only narrower lpm wide trenches arc completely tilled. The wider 3pm wide trenches arc partially~fXled per Figure 2a. After a RIE etch, the remaining ffl material along the side-walls of 3pm wide trenches acts as spacer mask during the liier'oxide etch. Oxide or dielectric is completely etched from the bottom of the 3@n substrate contact trenches (Figure 2b) pr...