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DENSE PACKAGING FOR HIGH SPEED CACHE MEMORY (FAST STATIC RAM) AND MAIN MEMORY (DRAM)

IP.com Disclosure Number: IPCOM000006739D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-28
Document File: 4 page(s) / 223K

Publishing Venue

Motorola

Related People

Ernel Winkler: AUTHOR [+2]

Abstract

In computer operation, a high speed intermediate cache memory enhances computation throughput. For example, on a RISC processor with a small on-chip pri- mary cache, a larger second level off-chip cache may be used. Cache memories may be used similarly with CISC processors. Instructions and data must flow to and from the FSRAM cache chips. For highest system through- put, the instruction and data interchange must occur in minimum access time for read and write. The goal is to bring to the processor the immanently needed instruc- tions and data contained in the off-chip cache with mini- mum package/interconnect related delay. As processors become faster packaging delays in cache access will pro- duce an increasing percentage of access delay. When data and instructions needed by the processor are not present when needed, the processor must wait. Address and data signals to and from each of the FSRAMs, pass through the packaging and interconnect The delay prob- lem is greater for off-chip drivers implemented in CMOS. Full receiver switching occurs only tier the signal reflects back from the end of the line (at the last memory in a daisy chain connection). By miniaturizing the memory packages, the round-trip board path can be significantly reduced.

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MOlVROLA INC.. Technical Developments Volume 18 March 1993

DENSE PACKAGING FOR HIGH SPEED CACHE MEMORY (FAST STATIC RAM) AND MAIN MEMORY (DRAM)

by Ernel Winkler and Jay Liu

INTRODUCTION

  In computer operation, a high speed intermediate cache memory enhances computation throughput. For example, on a RISC processor with a small on-chip pri- mary cache, a larger second level off-chip cache may be used. Cache memories may be used similarly with CISC processors. Instructions and data must flow to and from the FSRAM cache chips. For highest system through- put, the instruction and data interchange must occur in minimum access time for read and write. The goal is to bring to the processor the immanently needed instruc- tions and data contained in the off-chip cache with mini- mum package/interconnect related delay. As processors become faster packaging delays in cache access will pro- duce an increasing percentage of access delay. When data and instructions needed by the processor are not present when needed, the processor must wait. Address and data signals to and from each of the FSRAMs, pass through the packaging and interconnect The delay prob- lem is greater for off-chip drivers implemented in CMOS. Full receiver switching occurs only tier the signal reflects back from the end of the line (at the last memory in a daisy chain connection). By miniaturizing the memory packages, the round-trip board path can be significantly reduced.

  For main memory (DRAMS) applications, the delay issue is related to how much memory may be accessed in a specified time. Hi memory density for main mem- ory can therefore enhance access and system throughput.

  The packaging solution for high speed memory access (addressing delay and data or instruction transit delay) proposed by a number of people in the industry, is the implementation of stacked memory. The problem with these solutions is cost. A second problem, for FSRAM memory, is heat transfer.

  A lower cost stacked memory approach is described to achieve high speed and density needed in current and future memory systems.

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MATERIALS AND STEPS FOR

LOW COST MEMORY STbCK

Low cost materials and processes are incorporated in the process steps following:

1. Bond lead frames to the backplane board (both sides) and to the back of the chip boards-see Figures 1 and 2c. The chip carrier board shown in Figure 2b is rela- tively wide so as to interconnect to a backplane of equal width. The backplane must be wide enough to route the total number oSsignal leads. (In some RISC systems with cache memory, the total lead count into an 8 chip memory has reached 200 leads).
2. Bond heat spreader/fm to the back of the chip carrier boards with thermally conductive adhesive such as filed epoxy (Figure 2~). ;,
3. Complete die bonds, u&g thermally conductive mate- rial, to chip boards.
4. Complete wire bonds on each chip to its chip carrier board (Figure 2).
6. Complete the lead frame bond from the chip carrier board to the b...