Browse Prior Art Database

CONTROLLED SLEW RATE OUTPUT PAD

IP.com Disclosure Number: IPCOM000006740D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-28
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Philip McEntarfer: AUTHOR [+2]

Abstract

A classical problem in integrated circuit design is controlling the slew rate of digital output signals. Signals that are too slow result in low operation speeds and signals which are too fast result in such effects as EMI noise and ringing of signals due to transmission line effects. Typical CMOS processes result in uncontrolled edge rate variations of four or five to one over normal temperature, voltage, and process variation. Combine this with the addition of capacitive load variation and the problem is even more ditlicult. The described cir- cuits sense the output voltage and provide a feedback signal to control the output edge rate. Edge rate com- pensation is provided for varying capacitive loads as well as reducing process, temperature, and voltage sensitivity.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 2

0 M

MOTOROLA INC. Technical Developments Volume 18 March 1993

CONTROLLED SLEW RATE OUTPUT PAD

by Philip McEntarfer and Jeffrey Porter

  A classical problem in integrated circuit design is controlling the slew rate of digital output signals. Signals that are too slow result in low operation speeds and signals which are too fast result in such effects as EMI noise and ringing of signals due to transmission line effects. Typical CMOS processes result in uncontrolled edge rate variations of four or five to one over normal temperature, voltage, and process variation. Combine this with the addition of capacitive load variation and the problem is even more ditlicult. The described cir- cuits sense the output voltage and provide a feedback signal to control the output edge rate. Edge rate com- pensation is provided for varying capacitive loads as well as reducing process, temperature, and voltage sensitivity.

  The circuits use a feedback capacitor, known as a M&r capacitor, across a gain device to control the out- put edge rate. This is very similar to the way output slewing is controlled in an integrated operational ampli- tier. There are two basic topologies which can be used. The first is shown in Figure 1 and uses a separate Miller capacitor around both PMOS and NMOS devices. The slew rate of the output is determined by the current sources, I1 and 12, and the capacitors, Cl and C2. The second is shown in Figure 2 and uses only one capaci- tor which is alternately connected to either the NMOS or the PMOS device. In Figure 1 the controlling current source can be a simple resistor and, similarly, the resis- tors in Figure 2 can be active current sources. The resis- tor implementation can produce a circuit which dissi- pates no quiescent power which is sometimes critical in CMOS circuits. An active current source can be pro- duced which will provide better rejection of tempera- ture, process, and supply voltage than a resistor. The trade offs must be considered for a particular design or application.

  This type of circuit will allow for a larger output device for more DC drive while at the same time, due to the feedback, reducing the peak curr...