Browse Prior Art Database

JTAG CLOCK & CONTROL SIGNAL DISTRIBUTION SCHEME

IP.com Disclosure Number: IPCOM000006746D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-29
Document File: 6 page(s) / 217K

Publishing Venue

Motorola

Related People

Timothy R. Jones: AUTHOR

Abstract

This invention applies to integrated circuits which make use of boundary scan architecture. For informa- tion on JTAG boundary scan refer to the document enti- tled "IEEE Standard Test Access Port and Boundary- Scan Architecture, IEEE Std. 1149.1-9990" In typical sea-of-gates macrocell/gate arrays the cir- cuit is created solely by customizing the metal intercon- nect of these gates. Motorola's H4C family of CMOS arrays are a cross behveen gate arrays and standard cells in that they are sea-of-gates arrays which have the added capability of accommodating fully-diffused "big blocks: such as RAM's and MPU's. In Figures 1-3 a dotted lie marks the boundary between the core and periphery of an H4C array. The core consists of the sea-of-gates and big blocks. The periphery consists of I/O cells, or sites, which are typically configured as input, output or bidi- rectional buffers in order to interface the core logic to circuitry external to the array. When JTAG boundary scan methodology is used on an H4C array, I/O cells which are pinned-out are configured as Boundary Scan Cells (BSC's), which include some logic in addition to the aforementioned chip interface butlers. Figure 4 shows the logic. and I/O buffer portions of a bidirectional BSC, and the associated JTAG clock and control signals. This invention consists of a unique scheme for distributing these signals from their respective sources in the array core to all BSC's around the periphery ofthe chip.

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MOTOROLA INC. Technical Developments Volume ia March 1993

JTAG CLOCK & CONTROL SIGNAL DISTRIBUTION SCHEME

by Timothy R. Jones

DESCRIPTION

  This invention applies to integrated circuits which make use of boundary scan architecture. For informa- tion on JTAG boundary scan refer to the document enti- tled "IEEE Standard Test Access Port and Boundary- Scan Architecture, IEEE Std. 1149.1-9990"

  In typical sea-of-gates macrocell/gate arrays the cir- cuit is created solely by customizing the metal intercon- nect of these gates. Motorola's H4C family of CMOS arrays are a cross behveen gate arrays and standard cells in that they are sea-of-gates arrays which have the added capability of accommodating fully-diffused "big blocks: such as RAM's and MPU's. In Figures 1-3 a dotted lie marks the boundary between the core and periphery of an H4C array. The core consists of the sea-of-gates and big blocks. The periphery consists of I/O cells, or sites, which are typically configured as input, output or bidi- rectional buffers in order to interface the core logic to circuitry external to the array. When JTAG boundary scan methodology is used on an H4C array, I/O cells which are pinned-out are configured as Boundary Scan Cells (BSC's), which include some logic in addition to the aforementioned chip interface butlers. Figure 4 shows the logic. and I/O buffer portions of a bidirectional BSC, and the associated JTAG clock and control signals. This invention consists of a unique scheme for distributing these signals from their respective sources in the array core to all BSC's around the periphery ofthe chip.

  The special buffers for the JTAG clock and control signals and most of their metal interconnect reside in I/O sites in the periphery (Figures l-3).

  As shown in Figure 2, the CKDR signal drives a CKDRMID buffer, which resides halfway between the CKDRCCI and CKDRCC2 buffers, which are driven by CKDRMID. The CKDRCCl and CKDRCC2 each drive half of the JTAG I/O cells on the chip via the "CKDR ring? There is a physical cut in the CKDR ring within the TDO macro. However, closing the CKDR ring on the opposite side of the chip from TDO is impor-

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tant because it guarantees ,that, over any range of oper- ating conditions, there will never he race conditions/hold time violations when the peripheral BSC's are operated as one long shi register. This is true due to the fact that all I/O BSC's share a common clock (CKDR) net. Nor is there a "bus contention"# problem on the CKDR ring, due to the wide separation (roughly two sides of the chip) and minimal skew between the CKDRCCl and CKDRCC2 buffers which drive this ring.

  SHDR, UDDR, IMC and OMC are distributed essentially as shown in Figure 3 for SHDR. The SHDR signal drives two SHDR buffers, each of which drives roughly half of the JTAG II0 cells on the chip via the SHDR ring. Gap 1 and gap 2 are both actual physical cuts in the SHDR ring, unlike the gap in the CKDR ring. A break in these lines does not cause...