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GATE-OVERLAPPED ELEVATED SOURCE/DRAIN MOSFET

IP.com Disclosure Number: IPCOM000006747D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-29
Document File: 4 page(s) / 219K

Publishing Venue

Motorola

Related People

James R. Pfiester: AUTHOR [+4]

Abstract

Lightly-doped drain (LDD) structures are typically used to suppress hot-carrier effects in submicron CMOS devices [ 11. The conventional LDD spacer process con- sists of a low-dose source/drain implantation performed after polysilicon gate etch which is followed by the dep- osition and reactive-ion etch of a dielectric material to form a sidewall spacer offset for a subsequent high-dose source/drain implantation. The reduction in the lateral electric field results in lower substrate currents-and longer hot-carrier lifetimes. Optimization of the LDD struc- ture typicalIy requires higher LDD implantation doses than that which would correspond to minimum sub- strate current generation [2]. This is due to modulation of the series resistance caused by hot-carrier induced trapped charge over the LDD region. Since this LDD region resides outside the polysilicon gate, the trapped charge can push the current flow below the surface and degrade the gain of the device.

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MOTOROLA INC. Technical Developments Volume 18 March 1993

GATE-OVERLAPPED ELEVATED SOURCVDR~IN MOSFET

by James Ft. Pfiester, Carlos Mazur6, James D. Hayden, Howard C. Kirsch

  Lightly-doped drain (LDD) structures are typically used to suppress hot-carrier effects in submicron CMOS devices [ 11. The conventional LDD spacer process con- sists of a low-dose source/drain implantation performed after polysilicon gate etch which is followed by the dep- osition and reactive-ion etch of a dielectric material to form a sidewall spacer offset for a subsequent high-dose source/drain implantation. The reduction in the lateral electric field results in lower substrate currents-and longer hot-carrier lifetimes. Optimization of the LDD struc- ture typicalIy requires higher LDD implantation doses than that which would correspond to minimum sub- strate current generation [2]. This is due to modulation of the series resistance caused by hot-carrier induced trapped charge over the LDD region. Since this LDD region resides outside the polysilicon gate, the trapped charge can push the current flow below the surface and degrade the gain of the device.

Gate-overlapped LDD structures such as the ITLDD
[3] or LATID [4] have been proposed to provide improved hot-carrier reliability with lower series resist- ance. Due to the overlap of the vertical gate field with the LDD regions, a lower lateral electric field provides both lower substrate current as well as longer DC hot- carrier lifetimes. Any trapped charge or interface states which are generated under the polysilicon gate would have a smaller impact on altering the device series resist- ance as compared to the conventional LDD structure. Furthermore, the vertical gate fields result in an enhanced LDD surface concentration, which in turn lowers the device series resistance. Although the overlapped LDD structures provide improvements in gain and hot-carrier reliability, larger physical polysilicon gate lengths are required for a given electrical channel length as com- pared to the conventional LDD device. This can also result in an increase in the gate overlap capacitance by as much as 30% 151. As an alternative, the LDD region can be vertically integrated into an elevated source/drain MOSFET structure in which the overlapped region lies parallel to the polysilicon gate edges [6].

A new gate-overlapped elevated source/drain

50

MOSFET is proposed for a 0.25pm CMOS technol- ogy. Using disposable spacers to defme selective silicon deposition, a thin polysihcon liner is deposited between the elevated source/drain~$td polysilicon gate regions. This polysilicon liner, which is electrically connected to the gate electrode, results in fully-overlapped LDD regions while preserving the polysilicon gate pitch which is defined by the thicker gate regions. In this new struc- ture, the low-dose LDD implantation is performed after selective silicon deposition, thus resulting in ultra-shallow LDD junction depths. Comp...