Browse Prior Art Database

A LOW COST BUMPED THERMAL TEST CHIP ASSEMBLY

IP.com Disclosure Number: IPCOM000006755D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-30
Document File: 3 page(s) / 204K

Publishing Venue

Motorola

Related People

Tien-Yu Tom Lee: AUTHOR

Abstract

DESCRIPTION OF THE CONCEPT The side view of the bumped thermal test chip assem- bly is shown in Figure I. It is proposed to die bond an existing thermal test chip on the top side of an FR-4 board. The die bond material is a high-thermal- conductivity epoxy (for example: silver-filled epoxy). The I/OS from the test chip are connected to the board by wire-bonding. Most test chips have metal pads for wire bond. For a TAB version of test chip, wire-bond interconnections can apply to copper bumps (or gold bumps) which were positioned peripherally. In case of a flip-chip version of a test chip, which has solder bumps (PblSn) positioned peripherally, a wire-bonder using sol- der wire can connect these solder bumps to the board. In summary, an existing thermal test chip can be bonded to the board directly; its I/OS can be connected to the board by wires; no extra process is required prior to wire bonding.

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MO7VROLA INC. Technical Developments Volume 18 March 1993

A LOW COST BUMPED THERMAL TEST CHIP ASSEMBLY

by Tien-Yu Tom Lee

DESCRIPTION OF THE CONCEPT

  The side view of the bumped thermal test chip assem- bly is shown in Figure I. It is proposed to die bond an existing thermal test chip on the top side of an FR-4 board. The die bond material is a high-thermal- conductivity epoxy (for example: silver-filled epoxy). The I/OS from the test chip are connected to the board by wire-bonding. Most test chips have metal pads for wire bond. For a TAB version of test chip, wire-bond interconnections can apply to copper bumps (or gold bumps) which were positioned peripherally. In case of a flip-chip version of a test chip, which has solder bumps (PblSn) positioned peripherally, a wire-bonder using sol- der wire can connect these solder bumps to the board. In summary, an existing thermal test chip can be bonded to the board directly; its I/OS can be connected to the board by wires; no extra process is required prior to wire bonding.

  Figure 1 shows that the test chip is bonded on the top copper layer of the FR-4 board. The 1 oz/A2 copper on the board (on two sides) is - 1.4 mil thick. The FR-4 board is -62.5 mil thick. The desired bumping patterns (either peripheral- or area-bumps) arc built on the back of the board. The metallurgy of the bump is optimally determined by the flip-chip process. Four processes are currently available in Motorola for bump formation: SPS bipolar plated solder bump, the IBM-type evaporated solder bump (C4), the CMRC mechanical solder bump, and the ball bump technology (using wire bonder to form either solder bumps or gold bumps).

  Figure 1 shows two kinds of the flip-chip bump are built: the I/O bumps and the thermal bumps. The I/O bumps are separated from the copper layer (note: from the side view, it looks that the I/O bumps are on the copper layer). The thermal bumps arc grown on the copper layer and are used to simulate heat flow patterns for desired bumping patterns. Signals are transferred through the board by vias (either solid or hollow vi%).

The high-thermal-conductivity epoxy layer and the

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copper layer underneath the test chip are served as a good heat spreading medik To insure that the majority of power generated from the test chip is conducting to the back side of the board, additional dense thermal vias (along with the I/O vias) are constructed within the board thickness. These thermal vias are widely spread in the board to guarantee uniform heating on the back side of the board. Thermal vias may connect to the thermal flip-chip bumps as an option (see Figure 1). Once this bumped thermal test chipi,assembly is made, it can be bumped to a variety of substrates or packages (such as PGA, SOR QFR etc.) for testing and prototyping.

The following example illustrates the application of this concept.

EXAMPLE

  A silicon-based thermal test chip is 390x390 mil square and has eight 4x4 mil square bonding pads (for wir...