Browse Prior Art Database

LOW THERMO-MECHANICAL STRESS FLIP CHIP BUMPS

IP.com Disclosure Number: IPCOM000006759D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-30
Document File: 2 page(s) / 103K

Publishing Venue

Motorola

Related People

Jong-Kai Lin: AUTHOR [+5]

Abstract

One of the most important reliability issues in flip chip packaging is the thermo-mechanical stress which is caused by the mismatch of the coefficients of thermal expansion (CTE) between the chip and the substrate. This thermo-mechanical stress can be reduced either by using a substrate material whose CTE matches the device (Si or GaAs) or by increasing the spacing between the chip and the substrate.

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MO-LA INC. Technical Developments Volume 18 March 1993

LOW THERMO-MECHANICAL STRESS FLIP CHIP BUMPS

by Jong-Kai Lin, Bill Lytle, Tom Scharr, Ravi Sharma, and Ravi Subrahmanyan

  One of the most important reliability issues in flip chip packaging is the thermo-mechanical stress which is caused by the mismatch of the coefficients of thermal expansion (CTE) between the chip and the substrate. This thermo-mechanical stress can be reduced either by using a substrate material whose CTE matches the device (Si or GaAs) or by increasing the spacing between the chip and the substrate.

  The chip-to-substrate spacing depends on bump height. Bumps are typically grown by either plating or evaporation methods. Both processes are very time con- suming and require masking steps. A newly developed bumping process includes using a thermosonic wire ball bonder to form Au ball bumps on the chip or substrate (Figure 1). The Au ball bumps are then flip chip bonded to the substrate by applying thermal compressive force.

During the bonding operation, the Au bump's tail is compressed, leaving a relatively short bump. The final chip-to-substrate spacing therefore depends on the size of the ball in the bumping process and the compressive force in the bonding process. As the number of I/O bumps in each device increases, so does the thermal compressive force needed to bond the chip to the sub- strate. This increases the risk of damage to the chip, especially ifit is a GaAs device which is brittl...