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LOGIC CIRCUIT FOR SELECTING JUNCTION TEMPERATURES FOR ASIC CMOS RELIABILITY AND YIELD ENHANCEMENT

IP.com Disclosure Number: IPCOM000006782D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Jan-31
Document File: 3 page(s) / 160K

Publishing Venue

Motorola

Related People

Tomas Colunga: AUTHOR [+2]

Abstract

This discussion deals with an enhancement to a design methodology entitled 'Logic Circuit for ASIC Reliability and Yield Enhancement' (patent pending- docket no. SCO6873C) which provides control over the junction temperature of CMOS ASIC's, regardless of packaging technology. The general purpose behind the design methodology remains the same-to support the burn-in environment associated with device/package qualifications and to facilitate ongoing yield enhancement efforts. The circuit enhancement deals with the issue that certain packaging technologies associated with today's CMOS gate arrays, such as TAB, cannot be put into an oven to set the desired junction temperature. This dilemma is complicated by one of the main advantages of CMOS-low power. Circuit operation will be discussed by first describing the initial circuit followed by that which includes the enhancement.

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INC. Technical Developments Volume18 March 1993

LOGIC CIRCUIT FOR SELECTING JUNCTION TEMYERATURES FOR

ASIC CMOS RELIABILITY AND YIELD ENHAVCEMENT

by Tomas Colunga and David Lopez ~

1.0 INTRODUCTION

  This discussion deals with an enhancement to a design methodology entitled 'Logic Circuit for ASIC Reliability and Yield Enhancement' (patent pending- docket no. SCO6873C) which provides control over the junction temperature of CMOS ASIC's, regardless of packaging technology. The general purpose behind the design methodology remains the same-to support the burn-in environment associated with device/package qualifications and to facilitate ongoing yield enhancement efforts. The circuit enhancement deals with the issue that certain packaging technologies associated with today's CMOS gate arrays, such as TAB, cannot be put into an oven to set the desired junction temperature. This dilemma is complicated by one of the main advantages of CMOS-low power. Circuit operation will be discussed by first describing the initial circuit followed by that which includes the enhancement.

2.0 DESCRIPTION OF OPERATION

  The block diagram of the original circuit and its associated 'design verify' output waveform is shown by Fiie IA. The oscillator output serves as the clock which continuously sequences the design through its overall operation. The vector generator is triggered on the ris- ing edge of clock. The falliig edge of the clock latches the parity output which signifies whether the design oper- ated correctly for that given vector. The vector genera- tor has 2 modes of operation-verify design and verify parity. During design verify, all logic matrices get exhaustively stimulated-simultaneously. Ifall logic matri- ces function identically the 'verify design' portion of the output expected waveform will be continuously at a logic low as a result of the parity block. During parity verify the generator will stimulate the parity circuitry to ensure that it functions properly. It accomplishes this by intro- ducing mismatches to the parity circuitry which in turn cause the logic high pulses in the 'verify parity' portion of the output waveform. Having a characteristic waveform

consisting of a fLwed nuder of rising edges makes for a simpliiied design monitor&g scheme-a simple frequency counter can be used to a&mplish the task. Any prob- lem detected with the furictionality of the circuit will significantly change the odjput frequency.

  The enhanced circuit (additions are highlighted) and its associated expected dutput design waveform are shown by Figure 1B. Elevated junction temperatures are achieved by simultaneoukly switching all of the logic matrices in the design. The circuit additions include a variable oscillator, a multiplexer and, a binary up coun- ter (MODE). Every time the vector generator completes a full cycle it increments: the MODE binary counter. The MODE block controls whether the design is in a 'hot' or 'verify' mode of operation. F...