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P-CHANNEL LOAD FOR COMPLEMENTARY GaAS DCFL LOGIC

IP.com Disclosure Number: IPCOM000006796D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Feb-01
Document File: 2 page(s) / 93K

Publishing Venue

Motorola

Related People

William J. Ooms: AUTHOR

Abstract

This report describes a new logic family has been used on complementary GaAs. The goal is to achieve the fastest possible performance at low voltage (nomi- nal 1 volt supply) at a reasonably low power dissipation. Because of the extremely fast n-channel devices on GaAs (and slower p-channel devices), the P-load DCFL logic uses only n-channel devices as switching devices. How- ever, the logic swings are fully compatible with full com- plementary circuits.

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MOTOROLA INC. Technical Developments Volume 18 March 1993

P-CHANNEL LOAD FOR COMPLEMENTARY GaAS DCFL LOGIC

by William J. Ooms

   This report describes a new logic family has been used on complementary GaAs. The goal is to achieve the fastest possible performance at low voltage (nomi- nal 1 volt supply) at a reasonably low power dissipation. Because of the extremely fast n-channel devices on GaAs (and slower p-channel devices), the P-load DCFL logic uses only n-channel devices as switching devices. How- ever, the logic swings are fully compatible with full com- plementary circuits.

  Logic gates are built with various combinations of series and parallel n-channel devices with a p-channel pull-up device as shown in Figure 1. Essentially, a NOR gate is lie the traditional Direct Coupled FET Logic (DCFL) that is commonly used in n-channel only GaAs technologies. Whereas DCFL uses depletion mode devices as a constant current load element (with gate and source terminals shorted), the P-load DCFL uses a p-channel device operated as a current source. This avoids the need for an additional implant or more complex epi structores that are required for depletion mode devices on the same substrate. Other complex gates can obvi- ously be fabricated using a similar design style.

  An additional benefit of this logic family is that the current to the logic gate can be varied with diierent bias voltages (DCFL gates built with E/D devices have a fLxed current set by the size of the depletion device). More importantly, the current can be completely turned off for standby operation and power management.

  The plot in Figure 2 shows the unloaded inverter delay as a function of supply voltage with the bias pin grounded which results in'maximum current to the cir- cuit. Physical gate lengths;...