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HIGH RESOLUTION FRACTIONAL DIVIDER FOR LOW POWER, LOW COST MUSICAL TONE GENERATION

IP.com Disclosure Number: IPCOM000006805D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Feb-04
Document File: 2 page(s) / 99K

Publishing Venue

Motorola

Related People

James R. Webster: AUTHOR

Abstract

Musical tone generation in a paging system is most efficiently accomplished by circuitry which can be incor- porated into an existing support IC, as opposed to the addition of a special function IC. However, in order to minimize IC space requirements and current drain such circuitry must provide sutlicient tone resolution without resorting to complex methods such as frequency syn- thesis. Fractional division of a readily available crystal oscillator clock signal is the most efficient approach.

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INC. Technic'al Developments Volume 18 March 1993

HIGH RESOLUTION FRACTIONAL DIVIDER FOR LOW POWER, LOW COST MUSICAL TONE GENERATION

by James Ft. Webster

   Musical tone generation in a paging system is most efficiently accomplished by circuitry which can be incor- porated into an existing support IC, as opposed to the addition of a special function IC. However, in order to minimize IC space requirements and current drain such circuitry must provide sutlicient tone resolution without resorting to complex methods such as frequency syn- thesis. Fractional division of a readily available crystal oscillator clock signal is the most efficient approach.

  In paging systems, an alert tone generator circuit must be capable of high tone resolution under micro- controller control to generate aesthetically pleasing tones via an audio transducer. For example, from a 32kHz reference clock source one might want to generate 64 distinct frequencies between 2000Hz and 4000Hz. This would require divisors 157/8, 15%, 15% ,..., 8Y4, 81/s, and
8. Those twelve frequencies which are close to semi- tone boundaries could be used to form a melody. A post-scaler could be used to further divide the frequency to accommodate limited transducer bandwidth, etc. In order to realize a fractional divide ratio, the circuit would actually be alternating between two inregra/divide ratios at output cycle boundaries. This is manifested as phase noise, but the human ear perceives only the average fre- quency. Thus, for the 8% case, the reference clock would

be divided by 8 for 62.5% of the time and by 9 for 37.5% of the time.

  The dirhergeneraforcircuit horn a single accumula- tor fractional N divider (used in fractional N synthesizers for RF applications) can be adapted to realize this func- tion. Rather than controlling a two-modulus prescaler, the dither signal itself becomes the divided output sig- nal. A mathematical review will clarify this solution...