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# SIGMA DELTA MODULATOR WITH A RANDOM OUTPUT BIT STREAM OF SPECIFIED I/O AVERAGE RATIO

IP.com Disclosure Number: IPCOM000006814D
Original Publication Date: 1993-Mar-01
Included in the Prior Art Database: 2002-Feb-05
Document File: 5 page(s) / 202K

Motorola

## Related People

Itzhak Shperling: AUTHOR

## Abstract

A 2nd order digital Sigma-Delta (SD) modulator with a digital input representing a rational fraction (e.g. 9/16) produces at its output a bit stream at the clock rate with the "1" ratio equal the input fraction. In our case the problem is that with fractions like 9/16, the output bit stream is periodic with period of 16 or 32, so its frequency spectrum has many sideband tones. In our application-a functional-N synthesizer with divider modulus control as shown in Figure 2-we wish to con- trol the divider modulus with a random output bit stream with the correct "l"/"O" ratio so that its frequency spec- trum is spread and is not periodic.

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MOTOROLA INC. Technical Developments. Volume 18 March 1993

SIGMA DELTA MODULATOR WITH A RANDOM OUTbUT BIT STREAM OF SPECIFIED l/O AVERAGE RATId

by ltzhak Shperling

1. PROBLEM RESOLVED BY THE INVENTION:

A 2nd order digital Sigma-Delta (SD) modulator with a digital input representing a rational fraction (e.g. 9/16) produces at its output a bit stream at the clock rate with the "1" ratio equal the input fraction. In our case the problem is that with fractions like 9/16, the output bit stream is periodic with period of 16 or 32, so its frequency spectrum has many sideband tones. In our application-a functional-N synthesizer with divider modulus control as shown in Figure 2-we wish to con- trol the divider modulus with a random output bit stream with the correct "l"/"O" ratio so that its frequency spec- trum is spread and is not periodic.

2. DESCRlPTlON OF INVENTION:

A 2nd order digital Sigma-Delta modulator (SD- mod) is described in Figure 1, (see Figures attachment). It has a 20 bit input, 2 accumulators and 2 negative feedback loops and a quantizer that takes the Most Sig- nificant Bit, MSB, and produces a 1 bit output stream at
2.4MHz which is the clock rate clocking the D-Flip- Flops in the accumulators. The fraction of l's in the out- put bit stream is equal to the fraction represented by the 20 bit input word (say 9/16). This SD-mod controls a frequency divider by N (input 0) or N+l (input l), in a Fractional-N Frequency Synthesizer as shown in Fig- ure 2, thus producing the fractional part of the synthesizer's divide ratio (e.g. divide by 30 and 9116). The SD-mod must be random (non periodic) with a spread frequency spectrum (not concentrated in har- monic tones as in periodic signals). Ifthe output bit stream is periodic, as is the case without this invented modiica- tion, the synthesizer output will have sideband tones simi- lar to those in the SD-mod output (which essentially frequency modulates the synthesizer output).

The modification invented here is adding a small DC offset to the SD-mod input (set Least Significant Bit, LSB=l, adding 27-19) to the 9116 fraction) or possibly add 1 to the LSB carry-in of the adder in the first accumulator (doesn't work with the 2nd accumula-

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tar's adder carry-in). This :&mall input offset makes the SD-mod output random and its spectrum spread with much lower sideband tones. That assures necessary spec- tral purity of the Fraction+N synthesizer. See attached simulation results with and without the input DC offset (Figures 3,4): the improveinent in reducing the fust har- monic tone is over 20dB (this tone is the most critical, since it is least filtered by the synthesizer's low-pass loop filter).

BACKGROUND INFORMATlON ON TNIS INVENTlOW

This fractional-N synthesizer lits in a design of a digital receiver IC as described in a patent disclosure [Gailus 881. It describes a Zero-IF digital receiver Inte- grated Circuit (IC) design with an Automatic Frequency Control (AFC) feedback l&p f...