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A MULTI-STAGE SIGMA-DELTA CONVERTER ARCHITECTURE UTILIZING MULTIPLE SINGLE BIT OUTPUTS

IP.com Disclosure Number: IPCOM000006828D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2002-Feb-06
Document File: 2 page(s) / 130K

Publishing Venue

Motorola

Related People

Robert C. Ledzius: AUTHOR

Abstract

This paper presents a method for utilizing multiple output single bit stages to achieve a multi-bit sigma delta output that reduces output quantiaation noise without the matching requirements of a conventional multibit quantizer. Although the example is shown using a clas- sical 2nd order sigma delta modulator, the principle can also be applied to higher order modulators as well. The architecture is applicable to both Analog-to-Digital Converters @DC's) as well as Digital-to-Analog Con- verters (DAC's).

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MOTOROLA INC. Technical Developments Volume 19 June 1993

A MULTI-STAGE SIGMA-DELTA CONVERTER ARCHITECTURE UTILIZING MULTIPLE SINGLE BIT OUTPUTS

by Robert C. Ledzius

   This paper presents a method for utilizing multiple output single bit stages to achieve a multi-bit sigma delta output that reduces output quantiaation noise without the matching requirements of a conventional multibit quantizer. Although the example is shown using a clas- sical 2nd order sigma delta modulator, the principle can also be applied to higher order modulators as well. The architecture is applicable to both Analog-to-Digital Converters @DC's) as well as Digital-to-Analog Con- verters (DAC's).

1.0 THE SIGMA-DELTA MODULATOR

  Sigma-delta data converters are commonplace because of their abiity to exhibit linear performance by having only two qua&ration levels as well as their abit- ity to shape the quantization noise caused by this large 2-step output to higher frequencies out of the band of interest. This, coupled with the processing capabilities that continue to drive the bulk of the semiconductor industry, make them an excellent choice for Digital Sig- nal Processing (DSP) applications.

  It has been shown in the past that using well- developed, linearized continuous analysis, that the higher the order of the low-pas loop fnter, the more the feed- back is able to suppress the in-band quantization noise. The quantization noise can be suppressed even further by 6dB for every bit that is added to the quantizer or doubling of the quantization levels. Unfortunately, this also requires that the quantiaation levels be precisely matched to the foal desired resolution in order to real- ize the added performance.

  An example of a single bit classical second order sigma-delta DAC modulator used as a benchmark for evaluating the performance of the multistage architec- ture described in this paper is shown in Figure 1 and is oversampled by a factor of 256.

ZS.C-BYV-2-

FIGURE l.~~~~;~;bi;i~~&~ 2nd order sigma-

2.0 MULTI-STAGE SIGMA-DELTA ARCHITECTURE

  Breaking off the Srst integrator output stage into multiple second stages as in Figure 2 allows the inte- grated error signal to be worked on by each stage in an uncorrellated manner, provided that each stage is initialized to a different initial condition. Each one bit quantizer output is fed back to its respective 2nd inte- grator stage allowing the quantizer output to respond mainly to its own pattern. Additionally, all single bit out- put quantizers in the architecture are summed, scaled due to the added signal amplitude, and fed back to the input stage such that the t&t stage works on the com- posite error of the entire converter. Since the Signal con- tent of each of the quantizer output stages is perfectly correlated, the signal amplitude increases by about 6dB each time the number of one bit stages are doubled. The shaped quantization noise power, on the other hand, will increase by a maximum of 3dB each doubling time,...