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Browse Prior Art Database

GENERATION OF WATCHDOG FUNCTION USING PAL DEVICE

IP.com Disclosure Number: IPCOM000006830D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2002-Feb-06
Document File: 3 page(s) / 131K

Publishing Venue

Motorola

Related People

Nigel H. Chapman: AUTHOR [+2]

Abstract

A watchdog is a hardware circuit which is used to monitor the state of software execution of a processor. The processor is required to reset a hardware circuit, this circuit has a pre-deftned timeout period. Ifthe proc- essor does not reset the circuit before the timeout then the watchdog can either reset the processor or inform a controlling processor of the event (known as a host processor).

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Page 1 of 3

0 M MO-LA

INC. Technical Developments Volume 19 June 1993

GENERATION OF WATCHDOG FUNCTION USING PAL DEVICE

by Nigel H. Chapman and Timothy D. J. Smith

BACKGROUND TO INVENTION

  A watchdog is a hardware circuit which is used to monitor the state of software execution of a processor. The processor is required to reset a hardware circuit, this circuit has a pre-deftned timeout period. Ifthe proc- essor does not reset the circuit before the timeout then the watchdog can either reset the processor or inform a controlling processor of the event (known as a host processor).

  This is particulary important in systems which require high reliability and are likely to be remotely sited. With the Motorola base station this then allows remote reset

and re-activation of the relevant processor should a fail- ure in the field occur.

  Normally the watchdog circuit will consist of a monostable and D type flip-flop (see Figure 1). The monostable provides the timed element of the circuit where a resistor and capacitor provide an RC time con- stant, the duration of which defines the timeout period of the watchdog (i.e. the period in which the processor must reset the circuit). The D-type tlip flop is present to latch the occurrence of the watchdog event, and to pro- vide a means of resetting the watchdog under host proc- essor control. The latched event could then be read by a host processor and then suitable action taken.

DTYP~

> Flip

Flop

o- Watchdog output

( to host procesor )

Host Processor Reset

Figure 1 Existing watchdog circuit

SUMMARY OF PRIOR ART

  Currently each processor block uses the circuit of lems associated with fitting such circuits as Figure 1 on Fire 1 to perform the watchdog function. The more a PCB. This patent outlines one proposed method of processors you have the more additional circuitry you creating the watchdog function for a multi processor require for watchdog functions. As digital boards with arrangement with control derived from a single proces- larger quantities of processors are required, so do prob- sor (a host processor).

0 Motorola. inc. 1993 15

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0 M

MOTOROLA INC. Technical Developments Volume 19 June 1993

SUMMARY OF INVENTION

  To solve the above problems with watchdog circuits for multiple processors the circuit in Figure 2 will be used. A global clear signal CLR (active high state, this signal would be used for all watchdog blocks) is used to reset the circuit under host processor control. A truth table is defined below which displays the action of the circuit under its operational conditions. Note the clock input is not shown in the truth table, this will be...