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Method for variable land pitch to reduce interconnect misalignment caused by differences in thermal expansion rates in electronic packages and circuit boards

IP.com Disclosure Number: IPCOM000006853D
Publication Date: 2002-Feb-06
Document File: 3 page(s) / 52K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for variable land pitch to reduce interconnect misalignment caused by differences in thermal expansion rates in electronic packages and circuit boards. Benefits include improved thermal performance.

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Method for variable land pitch to reduce interconnect misalignment caused by differences in thermal expansion rates in electronic packages and circuit boards

Disclosed is a method for variable land pitch to reduce interconnect misalignment caused by differences in thermal expansion rates in electronic packages and circuit boards. Benefits include improved thermal performance.

Background

      The disclosed method addresses the problem of misalignment due to differences of thermal expansion rates of materials used in electronic packages and circuit boards.

              The conventional interconnect lands and joints of the substrates that are to be joined are aligned to each another at room temperature (see Figure 1). Misalignment occurs as the materials are brought up to reflow temperatures and the materials thermally expand. The conventional geometries of the interconnects and die/package dimensions allow acceptable levels of misalignment that do not compromise joint integrity. Misalignment is expected to become a more significant issue as interconnect geometries continue to reduce in size and/or as die/package sizes increase.

General description

The disclosed method reduces the coefficient of thermal expansion related misalignment that results from the processing of flip chip/C4 and/or surface mount packages (see Figure 2). The key elements of the method are:

•             Any of the individual factors or any combination of the factors listed below:

              -             A variable offset of interconnect array(s) between two substrates based on coefficient of thermal expansion differences of the materials

              -             A net reduction of as assembled interconnect misalignment

Advantages

      The technical advantage of the disclosed method is increased alignment accuracy between the solder balls/bumps and solder pads/lands at temperatures required to form interconnects.

Detailed description

              The disclosed method includes a process for preventing misalignment due to differences of thermal expansion rates of materials used in electronic packages and circuit boards. The process steps include:

1.           Characterize the coefficient for thermal expansion (CTE) for each...