Browse Prior Art Database

MODE SENSITIVE ADDRESS EXTENSION MODULE

IP.com Disclosure Number: IPCOM000006879D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2002-Feb-08
Document File: 2 page(s) / 87K

Publishing Venue

Motorola

Related People

Charles F. Studor: AUTHOR [+2]

Abstract

Most MCU address extension or paging schemes involve a register or port that select the upper address of the current instructions and data. These windowed schemes leave holes in the map so that page registers and peripherals can be accessed in any page.

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MO-LA INC. Technical Developments Volume 19 June 1993

MODE SENSITIVE ADDRESS EXTENSION MODULE

by Charles F. Studor and Eytan Hartung

PROBLEM SOLVED:

  Most MCU address extension or paging schemes involve a register or port that select the upper address of the current instructions and data. These windowed schemes leave holes in the map so that page registers and peripherals can be accessed in any page.

  The problem with these schemes is that they involve a lot of software overhead, inefficiently use memory and are not a smooth extension to the architecture.

  Also, many only allow a fixed size of memory. In cost sensitive systems this is not very cost effective because silicon area is spent for functionality that is not used.

SOLUTION:

  In the HC08 CPU, we have provided the hooks that create a much simpler address extension, from the pro- grammer's viewpoint. The address extension module out- put is dependent on which address mode the CPU is

using to access data.

* Extended and all Indexed modes use the address extension register for effective address calculation. * Immediate and Direct address modes access only the lower 64K address space.
* Program memory can be expanded in blocks of

64K. * Extension register with H:X becomes the lower

16 bits of a 24 bit index register.

Offset calculations carry through all 24 bits AIX (Add Immediate to Index) carries to extension register.

MOV ix-dr+, MOV dr-ix+, and CBEQ ix+ incre- ment all 24 bits.

Architecture is not limited to 24 bits Data space can be incremented in powers of 2.

IMPLEMENTATION:

  The CPU provides six control signals to an external module that describe the type of address mode as well as carries from modifications to...