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Method for an integrated heat spreader design with gold-plated nodules to control bond-line thickness for solder interface materials

IP.com Disclosure Number: IPCOM000006890D
Publication Date: 2002-Feb-08
Document File: 5 page(s) / 284K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an integrated heat spreader (IHS) design with gold-plated nodules to control bond-line thickness (BLT) for solder interface materials. Benefits include improved reliability, ease of manufacturing, and thermal performance.

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Method for an integrated heat spreader design with gold-plated nodules to control bond-line thickness for solder interface materials

Disclosed is a method for an integrated heat spreader (IHS) design with gold-plated nodules to control bond-line thickness (BLT) for solder interface materials. Benefits include improved reliability, ease of manufacturing, and thermal performance.

Background

      Increasing amounts of heat energy are produced during the application of microprocessor chips. As a result, solder thermal interface materials (STIMs) are utilized with increasing frequency. However, utilizing the conventional stack-up and reflow processing for the STIM and IHS (see Figure 1) variation in BLT is observed.  In addition, BLT control using sealant volume, perform size, and processing conditions can lead to great variations and a narrow reflow-processing window. STIM applied to a nickel-plated IHS does not wet the surface resulting in voiding and physical and thermal degradation of the STIM/IHS interface post reliability.  Gold is utilized to increase the wetting of the solder to the heat spreader interface.

      3-4 mils of substrate warpage during sealant cure has led to OLGA flip-chip packages with no sealant material between the IHS and substrate. These packages delamininate and fail to meet  thermal performance targets.  Adding spacers to the IHS lip and/or substrate interface ensures sealant is present to attach the substrate and IHS and maximum thermal performance. (Figure 4)

      The conventional IHS is sealed to the package by the following steps (see Figure 2):

1.           Dispense sealant onto the substrate

2.           Dispense flux onto the die

3.           Pick and place a solder preform onto the die
4.           Dispense flux onto the solder perform
5.           Place the IHS and clip it on top of the die
6.           Reflow the thermal interface solder

7.           Cure the sealant adhesive

8.           Remove the spring clip

Description

              The disclosed method includes an IHS with one or more .5-mil to10-mil or 15-µm to 250-µm bumps/spacers, or gold-plated nodules, stamped onto the top or cavity surface of the IHS to control Indium solder BLT (see Figures 3). Nodules added to the cavity surface reduce BLT variation (distance of the die to the cavity of the IHS), IHS tilting, and thermal performance variation. This configuration eliminates the dependency on the following factors:

•             TIM filler particle size for BLT control or perform size

•             Sealant dispense weight

•             Clip for...