Browse Prior Art Database

JTAG/DEBUG INTERFACE

IP.com Disclosure Number: IPCOM000006953D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2002-Feb-12
Document File: 3 page(s) / 170K

Publishing Venue

Motorola

Related People

Jay Hartvigsen: AUTHOR [+4]

Abstract

FIELD OF THE INVENTION This invention is an improved method for using the JTAG port as a means of communicating with a CPU which includes a debug mode of operation. Debug mode is a means by which a development tool can control the operation of and enhance the debugging of a computer based system.

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MOTOROLA INC. Technical Developments Volume 19 June 1993

JTAG/DEBUG INTERFACE

by Jay Hartvigsen, Tony Cheng, Eric Hoang and Buddy Broeker

FIELD OF THE INVENTION

  This invention is an improved method for using the JTAG port as a means of communicating with a CPU which includes a debug mode of operation. Debug mode is a means by which a development tool can control the operation of and enhance the debugging of a computer based system.

BACKGROUND OF THE INVENTION

  In order to debug increasingly complex micropro- cessors and microcomputers many of them have been designed with special debug modes of operation. This allows a development tool to control the operation of the processor without degrading the properties of sig- nals going into and out of the processor. These debug modes have the following goals:

1. Provide non-intrusive debugging.
2. Minimal silicon area to implement a debug inter- face with the processor.
3. Minimal pin count for debug mode interface.
4. Fast data transfer rate for upload/download memory.
5. Allow the development tool to read and write memory and registers.
6. Start and stop execution from appropriate debug commands.

  In the prior art, a debug mode was implemented on the MC68300, MC68HC16, MC56000 and the MC88304 families. The debug mode interface on the 300 and HC16 families has the disadvantage that it requires three addi- tional pins on the package. The debug mode interface on the 56000 and 88304 families has the disadvantages that it requires five additional registers, uses 4K bytes of the processor memory map (intrudes on the users mem-

ory map), and provides only a half duplex serial interface.

SUMMARY OF THE INVENTION

The objective of the present invention is to mini-

0 Motorola. 1°C. 1993

mire the drawbacks in the prior art. This is accomplished in the following ways:

1. Adds no pins to the package beyond what is needed for the JTAG interface.
2. Adds only two additional JTAG registers. (Lower silicon area)
3. Uses none of the processor memory map. (Non-intrusive)
4. Provides a full duplex serial interface to improve performance over the 56000 and 88304 by an estimated 10 to 15%. (Faster data transfer rate)

DESCFWTION OF THE INVENTION

  This invention combines the best of the prior art by using the JTAG port to provide a means of communi- cating with a CPU in debug mode. Two additional test data registers are required in the JTAG logic together with CPU interface control logic.

  The first added JTAG test data register is called the DEBUG-DATA register. It receives serial data from the JTAG test data input and transfers it to the CPU following the JTAG Update-DR state. It is also loaded with data from the CPU at the JTAG Capture-DR state so that data can be shifted out serially when the next data is shied in. This register is also part of the CPU register set but is available only when the CPU is in a special debug mode of operation.

  The second JTAG test data register provides the addi- tional status a...