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CIRCUIT TO CHANGE CLOCK SPEED WITHOUT LOSS OF TIMING

IP.com Disclosure Number: IPCOM000006962D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2002-Feb-12
Document File: 1 page(s) / 57K

Publishing Venue

Motorola

Related People

Anselm Sequelra: AUTHOR

Abstract

High data rate pa&g stations need to maintain accu- rate timing for simulcast purposes. This timing can be derived from a Global Positioning System (GPS) receiver. The GPS receiver provides an accurate 1 pulse per sec- ond (1 pps). The 1 pps is used to derive the sample clock for a DSP which produces the modulating signal for the transmitter.

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MOTOROLA INC. Technical Developments Volume 19 June 1993

CIRCUIT TO CHANGE CLOCK SPEED WITHOUT LOSS OF TIMING

by Anselm Sequelra

   High data rate pa&g stations need to maintain accu- rate timing for simulcast purposes. This timing can be derived from a Global Positioning System (GPS) receiver. The GPS receiver provides an accurate 1 pulse per sec- ond (1 pps). The 1 pps is used to derive the sample clock for a DSP which produces the modulating signal for the transmitter.

  When a paging channel must be shared by different paging protocols, it may be necessary to change the sam- ple clock rate. The sample clock rate is typically a multi- ple of the baud rate.

  The circuit shown in Figure 1, allows switching between two sample clock rates without losing sync with the lpps. This maximizes paging throughput and pre- vents short-term failure of the GPS receiver from affect- ing system operation.

  A programmable counter is used as a 'main divider' to divide the reference clock (16.8MHz) to produce either 5OKHz or 48KHz. A select line is used to choose the

required load value for the counter.

  The output of the main divider is used to clock a programmable module counter. The select lie chooses a modulus of either 25 or 24. When the main divider produces a SOKHz output the counter modulus should be 25. When the main divider produces a 48KHz out- put the counter modulus should be 24. This causes a carry out of the counter every 0.5 ms, regardless of the clock rate.

  A D-flip/flop...