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DYNAMIC PRIORITIZATION OF LOADS AND STORES FOR HIGH PERFORMANCE RISC ENGINES

IP.com Disclosure Number: IPCOM000006986D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-14
Document File: 3 page(s) / 201K

Publishing Venue

Motorola

Related People

Kara Basden Pepe: AUTHOR [+2]

Abstract

Buffering memory accesses from issue time to cache/memory access time is a feature which high performance microprocessor implementations are starting to include. The buffers effectively decouple instruction issue from cache/memory availability. Per- formance is improved since fewer instances of instruc- tion issue stalling occur. The addition of memory access buffers may require the microarchitecture to use a prioritization algorithm to choose the order the buffered accesses are executed.

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MOTOROLA INC. Technical Developments Volume 20 October 1993

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DYNAMIC PRIORITIZATION OF LOADS AND STORES FOR HIGH PERFORMANCE RISC ENGINES

by Kara Basden Pepe and Bill Moyer

  Buffering memory accesses from issue time to cache/memory access time is a feature which high performance microprocessor implementations are starting to include. The buffers effectively decouple instruction issue from cache/memory availability. Per- formance is improved since fewer instances of instruc- tion issue stalling occur. The addition of memory access buffers may require the microarchitecture to use a prioritization algorithm to choose the order the buffered accesses are executed.

  A prioritization algorithm for buffered memory accesses which achieves maximum performance for advanced microprocessor architectural features was developed for the MC88110. The prioritization algo- rithm dynamically adjusts to the state ofthe machine on a cycle-by-cycle basis. It achieves maximum per- formance by reacting quickly to support data stream- ing, hit-under-miss, and precise exception features. An explanation of these architectural features, the types of memory accesses of the MC88110, and the dynamic prioritization algorithm and its benefits are presented below.

tion are not as common as for load instructions. A procedure call contains an example of a store depend- ency. Loads which are typically issued at the end of a procedure call are dependent upon the stores issued at the beginning ofa procedure call. Both the stores and loads are accessing the same memory location, therefore, the stores must complete so the loads can access the new data in that memory A short proce- dure issues the store accesses and the load accesses close together in time. The load accesses may begin issuing before the store accesses have completed. This results in load-to-store dependencies which may delay the load completing which, in turn, may result in an instruction issue stall. The frequency of load- to-store dependencies described is directly related to the store latency and will vary from one micro- architecture to another.

INTRODUCTION:

THE REQUIREMENT OF PRlORlTlZATlON ALGORITHMS

TYPES OF MEMORY ACCESSES:

  There are two basic types of memory accesses, loads and stores. Loads retrieve data horn memory and place them in registers for future instructions to use. Typically, some instructions, issued after the load, are dependent upon the data which the load is retriev- ing From memory. If data required for execution of an instruction is not available in the register file, instruction issue is stalled in many microprocessors. Any stall of a load completing its data retrieval, there- fore, could potentially result in stalling instruction issue, thus lowering processor performance.

  Store instructions copy register data into mem- ory. Dependencies on store instructions which cause another instruction to stall from issuing or comple-

0 MOtOrOl*, 1°C. 1993

  Buffering ofmemory accesses can re...