Browse Prior Art Database

MASKLESS WELL PROCESS

IP.com Disclosure Number: IPCOM000006991D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-14
Document File: 4 page(s) / 162K

Publishing Venue

Motorola

Related People

Robert Reuss: AUTHOR

Abstract

The success of this method depends on several factors: .NMOS short channel effects are minimal, thus P-well surface doping can be relatively low (4E17/cm').

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MOTOROLA INC. Technical Developments Volume 20 October 1993

MASKLESS WELL PROCESS

by Robert Reuss

The success of this method depends on several factors:

.NMOS short channel effects are minimal, thus P-well surface doping can be relatively low (4E17/cm').

l P-well doping is a function of P-epi doping and P buried layer up-diffusion, not just P-well implant dose.

l NMOS Vt implant helps set surface concentration.

l Phosphorous (N-type) implant dose not very heavy (<E16/cmZ) to keep N-well doping low (about lE16/cm3) to minimize NPN collector-base capacitance.

l N-well drive is long (to reach to N+ buried layer) which lowers N- doping at the epi-surface. 'NMOS in a BiCMOS flow has a relatively high threshold voltage and body effect. Lower P-well doping due to a blanket phosphorous N-well implant would result in improved device characteristics.

INTRODUCTION

  Over the last several years BiCMOS has become an important technology for SRAM memory and mixed mode circuits (analog and digital functions on the same chip). One limitation which is always considered when both CMOS and BiCMOS can be applied to the design is the additional cost associated with the extra processing needed to produce a BiCMOS chip. To achieve huther inroads in the mar- ket place, BiCMOS processes will need to either increase the hmctionality possible and/or reduce the cost differential relative to CMOS. Described below is a process simplification which can reduce both complexity and defect density and ultimately the cost to produce a BiCMOS wafer.

BACKGROUND

  Mainstream BiCMOS processes incorporate N+ and P buried layers in p-substrate wafers to provide moderate to high performance bipolar devices. To integrate the CMOS devices a lightly-doped (<lE16/cmJ) epi layer is grown (Figure 1) and subsequently implanted to provide N-wells (for ver- tical NPN's lateral PNP's, PMOS and resistors) and P-wells (NMOS). The well doping is determined by the separate masked implantation of phosphorous
(P) for N-wells and boron (B) for P-wells.

  This dual well process module requires a series of photo, etch, deposition, and oxidation steps. Not only do these steps increase process complexity, they can create defects which are subsequently observed as degraded gate oxide quality and yield loss. A sim- ple maskless well implant which resulted in the desired well dopant concentrations would provide a cost reduction of at least 10%. This can be accom- plished by a maskless phosphorous implant. This would leave the N-well unchanged compared to the existing process, but the P-well doping would be lighter because it would now be implanted with phos- phorous (N-type) rather than boron (B-type).

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RESULTS

  Figure 2 compares the P-well doping profiles for the standard and proposed maskless well process after the field oxidation module. Note that only the upper surface ofthe well is (barely) N-type. The P-epi and boron up-diffusion have over-compensated the phos- phorous imp...