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MULTIPLEXING OF MULTIPLE LEVE/EDGE TRIGGERED INTERRUPTS AT SINGLE INPUT

IP.com Disclosure Number: IPCOM000007005D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-15
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Zoran Ulicevic: AUTHOR

Abstract

Hardware design engineers are ohen squeezed between ever growing requirements and silicon limi- tations. One specific area, that this article is dealing with, is how to "increase" number of available inter- rupt lines of a microprocessor by multiplexing them using simple RC circuit.

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MOTOROLA INC. Technical Developments Volume 20 October 1993

MULTIPLEXING OF MULTIPLE LEVEUEDGE TRIGGERED INTERRUPTS AT SINGLE INPUT

by Zoran Ulicevic

  Hardware design engineers are ohen squeezed between ever growing requirements and silicon limi- tations. One specific area, that this article is dealing with, is how to "increase" number of available inter- rupt lines of a microprocessor by multiplexing them using simple RC circuit.

  Main idea is described using four interrupt lines, as is shown in Figure 1, but number of lines are not limited by this circuit. IRQs shown are input sig- nals assumed to be TTL levels and active low. When none of this signals is asserted circuit is in an idle state. All IRQ signals are high, and all NAND inputs are high via pull-up resistors Rl through R4. As a result of all inputs true (high), output of NAND gate, signal "interrupt:' is low (negated high).

  When any of input signals, IRQl for example, gets asserted, goes low, low level voltage will instantaneously discharge corresponding capacitor, Cl in this example. Thus, low levebwill be applied on one of the NAND inputs and its output, "inter- rupt:' will toggle to high, representing not true con- dition. Discharged capacitor Cl will start charging via resistor Rl and VCC with RlCl timing constant, regardless of the state of IRQl. When voltage on right side of Cl reaches triggering point for NAND gate to recognize it as high, all inputs will again be high resulting in "interrupt" to go low again. At that moment circuit is ready to react on another input. Duration of "interrupt" signal, Tl in Figure 2 for our example, is predetermined by the value of corresponding Rs and Cs and can easily be altered.

  While the described RC mechanism is well known note should be put here that presented cir- cuit works as self reset, meaning that one of inputs

can stay asserted and will not mask recognition of another one. That is why it can react e...