Browse Prior Art Database

POSPBL-POLY SPACER POLY BUFFERED LOCOS (A Novel Trench + Shallow Element Isolation Concept)

IP.com Disclosure Number: IPCOM000007006D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-15
Document File: 3 page(s) / 143K

Publishing Venue

Motorola

Related People

Juergen Foerstner: AUTHOR [+3]

Abstract

Sub-micron BiCMOS requires a deep trench iso- lation for the Bipolar devices in order to allow for adequate scaling opportunity, while reducing para- sitic capacitances and thereby reducing gate delay at low power operations. At the same time the CMOS portion of the circuit requires an isolation scheme, that is simple scalable as well and supports a small WetT, with minimal encroachment (.6 micron at the .5 micron BiCMOS level), while supporting > 7 volts breakdown for both N+ to N+ and P+ to P+ S/D ditlG- sions at minimum device spacing for dense SBAM's. The novel POSPBL approach achieves the above cri- terion. The trench topography needs to be sutBciently planar to prevent stringer formation at subsequent poly silicon and metallization layers, while the net stress being transmitted by the trench into the adja- cent silicon islands must be sufficiently low to pre- vent the formation of defects and Bandgap lowering in the Bipolar device structure, which would lead to gain modification as a function of trench spacing. The CMOS shallow element, while also being con- strained by topography and stress issues is saddled with the additional requirement of maintaining its actual size during subsequent processing steps.

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MOTOROLA INC. Technical Developments Volume 20 October 1993

POSPBL-POLY SPACER POLY BUFFERED LOCOS (A Novel Trench + Shallow Element Isolation Concept)

by Juergen Foerstner, Margaret Huang and Sam Sundaram

  Sub-micron BiCMOS requires a deep trench iso- lation for the Bipolar devices in order to allow for adequate scaling opportunity, while reducing para- sitic capacitances and thereby reducing gate delay at low power operations. At the same time the CMOS portion of the circuit requires an isolation scheme, that is simple scalable as well and supports a small WetT, with minimal encroachment (.6 micron at the
.5 micron BiCMOS level), while supporting > 7 volts breakdown for both N+ to N+ and P+ to P+ S/D ditlG- sions at minimum device spacing for dense SBAM's. The novel POSPBL approach achieves the above cri- terion. The trench topography needs to be sutBciently planar to prevent stringer formation at subsequent poly silicon and metallization layers, while the net stress being transmitted by the trench into the adja- cent silicon islands must be sufficiently low to pre- vent the formation of defects and Bandgap lowering in the Bipolar device structure, which would lead to gain modification as a function of trench spacing. The CMOS shallow element, while also being con- strained by topography and stress issues is saddled with the additional requirement of maintaining its actual size during subsequent processing steps.

  A simple/novel isolation scheme POSPBL developed for the .5 micron BiCMOS baseline trench isolation process appears to address all of the isola- tion problems identified above. In the region of the trench the replacement of the 2 step (thermal liner followed by deposited liner) with a much simpler thicker thermal liner only in conjunction with the removal of the poly encapsulation process (PEPBL) or the even more complex nitride spacer process (FMPBL), which were designed to limit oxygen dif- fusion in both the trench (bipolar region) as well as the shallow LOCOS element (CMOS region). A simple poly spacer did result in deeper oxide isola- tion in the MOS region and thereby improved ditfu- sion punch through characteristics compared to nitride spacer or poly encapsulated scheme. The

P+-P+ punchthrough voltage for 0.8 micron drawn field width at 1 micro ampere was 9 V for POSPBL compared to 2 V for PEPBL and FMPBL. This clearly shows the longer iso...