Browse Prior Art Database

SHIFTED CLOCKS FOR ASIC's

IP.com Disclosure Number: IPCOM000007008D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-18
Document File: 2 page(s) / 77K

Publishing Venue

Motorola

Related People

Eugene Ii. Gruender Jr.: AUTHOR [+2]

Abstract

In designing an ASK (Application Specific Inte- grated Circuit) for use in synchronous circuits with high-speed digital systems, e.g. those running at 40 Mhz or higher, two problems are encountered.

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MOTOROLA INC. Technical Developments Volume 20 October 1993

SHIFTED CLOCKS FOR ASIC's

by Eugene Ii. Gruender Jr. and Douglas R. Kraft

  In designing an ASK (Application Specific Inte- grated Circuit) for use in synchronous circuits with high-speed digital systems, e.g. those running at 40 Mhz or higher, two problems are encountered.

  First, today's processors ohen have internal phase-lock loop circuits that allow them to run faster internally than the external clock and to use clock edges not seen outside the processor chip. They ohen use these unseen edges as the sample times for sig- nals from external devices.

  Second, once the ASIC is designed, the typical times for delays must be multiplied by factors to give minimum and maximum delay times for the signal paths through the ASIC. Typical times might be factors of .5 to 1.85 to allow for heat, voltage, and manufacturing variations. This means that a nomi- nal delay of 1Ons could be as little as 5ns or as much as 18Sns. At 50 Mhz, with a clock period of 20ns, this makes a synchronous state machine very diffi- cult to design.

  In the case of the Motorola 88110 RISC proces- sor running at 50 Mhz, the clock period is 20ns. Referring to Figure 1, the clock and timing require-

ments are set forth as follows. The clock is high for lOns, then goes low At llns, a sampling period begins for inputs to the processor. This window closes at 17ns. At 20ns, the clock' again goes high, and the cycle repeats.

  If a typical delay...