Browse Prior Art Database

IMPROVEMENT OF SILICON ON INSULATOR WAFER SURFACE QUALITY

IP.com Disclosure Number: IPCOM000007011D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-18
Document File: 2 page(s) / 128K

Publishing Venue

Motorola

Related People

Robert H. Reuss: AUTHOR [+4]

Abstract

Silicon on insulator (SOI) has been used for many years for special applications. The major SOI tech- nology has been silicon on sapphire (SOS) which has been used in military and space programs because of radiation tolerance (1). SO1 has found only limited applications because of its higher cost. The increased cost is the result of significantly higher wafer prices (because of complex manufacturing) and also lower process yield because of defects. Recently there has been a resurgence of interest in SOI for applications such as high temperature electronics (2), high voltage electronics (3), and very low volt- age electronics (4).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 2

0 M

MOTOROLA INC. Technical Developments Volume 20 October 1993

IMPROVEMENT OF SILICON ON INSULATOR WAFER SURFACE QUALITY

by Robert H. Reuss, Donald Hughes, Juan Carrejo and Ray Wells

tion followed by a Si implant and anneal to elimi- nate defects (1). The Si film thickness ins each case is 100-200 nm on either an insulating layer of Si02 or sapphire.

  Atomic force microscopy was used to determine the surface roughness (5). The figure compares sur- face roughness for bulk Si with SIMOX and PACE wafers. Note that the TFSOI samples have roughness in excess of 2nm. Published data (5) demonstrates detrimental effects for surface roughness of even
0.5-1.0 nm.

BACKGROUND

  Silicon on insulator (SOI) has been used for many years for special applications. The major SOI tech- nology has been silicon on sapphire (SOS) which has been used in military and space programs because of radiation tolerance (1). SO1 has found only limited applications because of its higher cost. The increased cost is the result of significantly higher wafer prices (because of complex manufacturing) and also lower process yield because of defects. Recently there has been a resurgence of interest in SOI for applications such as high temperature electronics
(2), high voltage electronics (3), and very low volt- age electronics (4).

  The renewed interest is based on the attractive electrical features that SO1 offers as well as improved material manufacturing and defectivity which will provide reduced cost. Thin film (C 100nm) SO1 (TFSOI) has received most ofthe attention because it could be the technology of choice in the ULSI era beyond 0.25um design rules (Ref 4). However, the material quality constraints become even more rig- orous. Surface roughness has been shown to result in lower gate oxide integrity and reduced perform- ance because of degraded mobility (Ref 5). Signih- cant effects are noted for roughness of only 0.5 nm more than virgin wafers. Thus, ifTFSO1 is to become a mainstream technology, not only will manufactur- ing costs and material defects be major issues, but also surface roughness must be minimized.

SOLUTION

  As indicated above, ,none of the TFSOI wafers receive any huther processing atler the SO1 struc- ture is formed. However, for conventional bulk Si wafers a them-mechanical polish is the final manu- facturing operation. Since TFSOI wafers h...