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Browse Prior Art Database

REFERENCE BASED CLOCK ENABLE

IP.com Disclosure Number: IPCOM000007027D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-19
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Patrick J. Svatek: AUTHOR [+2]

Abstract

For a microcontroller with imbedded EEPROM, a voltage greater than the CMOS VDD is required for read as well as write and erase operations. This voltage is generated by a self contained on chip charge pump. The charge pump includes an oscillator as well as the pumping circuits and the charge storage element. To achieve the lowest current when oper- ating in a low power mode, the charge pump must be turned off along with the chip oscillator and the system clocks. If the microcontroller is required to resume operation with the first system clock upon returning from low power mode and that the first operation afier returning from low power mode may be an EEPROM access, it is necessary to inhibit the system clocks until the charge pump has reached the minimum voltage level required for correct EEPROM operation. In addition it is desired that the chip oscillator be allowed to start up and stabi- lize during this time so as to not impose any addi- tional latency when returning from low power mode.

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MOTOROLA INC. Technical Developments Volume 20 October 1993

REFERENCE BASED CLOCK ENABLE

by Patrick J. Svatek and Thomas L. Portlock

  For a microcontroller with imbedded EEPROM, a voltage greater than the CMOS VDD is required for read as well as write and erase operations. This voltage is generated by a self contained on chip charge pump. The charge pump includes an oscillator as well as the pumping circuits and the charge storage element. To achieve the lowest current when oper- ating in a low power mode, the charge pump must be turned off along with the chip oscillator and the system clocks. If the microcontroller is required to resume operation with the first system clock upon returning from low power mode and that the first operation afier returning from low power mode may be an EEPROM access, it is necessary to inhibit the system clocks until the charge pump has reached the minimum voltage level required for correct EEPROM operation. In addition it is desired that the chip oscillator be allowed to start up and stabi- lize during this time so as to not impose any addi- tional latency when returning from low power mode.

system clocks. A feature of the microcontroller is a low power mode such that the chip oscillator and clock module are shut down, the level detection cir- cuits are preconditioned, and the charge pump may either be shut down or remain active. When the low power mode is deactivated the charge pump, the chip oscillator and ,the level detection circuits are enabled. The system clocks remain inhibited until the level detection circuit determines that the charge pump output has reached the required voltage for EEPROM operation. When this voltage level has been detected the system clocks are enabled and the microcontroller ca...