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Browse Prior Art Database

DIGITAL CLOCK PRESCALER

IP.com Disclosure Number: IPCOM000007039D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-20
Document File: 2 page(s) / 134K

Publishing Venue

Motorola

Related People

David Gurney: AUTHOR [+3]

Abstract

The described invention provides an efficient and versatile method of obtaining a desired clock rate from an arbitrary system clock. The method is completely synchronous, uses very little hardware, is extremely low power, and is very manufacturable and reliable. The structure is optimized for ASIC implementation, and can further be made program- mable to accommodate different systems. It is a direct and simple replacement for a complex phase locked loop, which would require many gates if implemented digitally, or several external components to imple- ment in analog circuitry.

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MOTOROLA INC. Technical Developments Volume 20 October 1993

DIGITAL CLOCK PRESCALER

by David Gurney, Jim Kelton and Steve Kuffner

  The described invention provides an efficient and versatile method of obtaining a desired clock rate from an arbitrary system clock. The method is completely synchronous, uses very little hardware, is extremely low power, and is very manufacturable and reliable. The structure is optimized for ASIC implementation, and can further be made program- mable to accommodate different systems. It is a direct and simple replacement for a complex phase locked loop, which would require many gates if implemented digitally, or several external components to imple- ment in analog circuitry.

  The described clock prescaler adapts near mul- tiple fractions ofthe external system clock for use in internal digital circuitry. For example, suppose that a (12.288 MHz) needed to be derived li-om an external
19.2 MHz system clock. Thus, a 16125 multiplier ratio (16/25 x 19.2 MHz = 12.288 MHz) is desired in the system. The prescaler essentially multiplies the input clock signal by the fraction m/n, with the restrictions below. The quantity n can be any num- ber (described below), without limit. The quantity m must be a power of two, and must be less than n. Furthermore, the output of the prescaler will be ris- ing edge symmetric (have evenly spaced rising edges) afier log2 (m) divide by two operations. In some cases, these clock edges,must be evenly spaced to reconstruct the digitally sampled outputs without distortion. Suppose that there are three divide by two operations between the clock prescaler output and the system output sample clock (to the DACs), so in this case, m is restricted to be less than or equal to 8 (ms23 = (1,2,4,8)). Note that n can be any integer multiple of 'h if operation is allowed off both edges of the clock (otherwise it must be an integer). This is equivalent to easing the restriction on m to be twice that described above (m's2m). In effect, a sort of clock doubling is employed by oper- ating off both clock edges, where half cycles of the input clock may be utilized to produce the desired average frequency at the output.

0 Motorola. Inc. 1993

  In the above system, a 16/25 multiplier (where m&l6 and n=25, or equivalently a 802.5 ratio, where m=8 and n=12.5) is obtained with the circuit in Figure 1. Note that the circuit is completely synchronous, and is therefore highly reliable. The general concept is to output 8 (m) clock cycles for every 12.5 (n) input clock cycles, such that the aver- age frequency of the output clock is equal to exactly the desired (12.288MHz) rate. Note that as long as the span of periodicity (the number of output cycles it takes to repeat) does not exceed 8 (m) cycles, the system will be able to use the scaled clock output properly. As mentioned before, since n is a non- integer, operation of both clock edges must be employed. The circuit in Figure 1 utilizes both edges ofthe i...