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REDUCED CAPACITANCE AND BASE-RESISTANCE NPN FOR CMOS-BASED BiCMOS

IP.com Disclosure Number: IPCOM000007067D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2002-Feb-22
Document File: 3 page(s) / 140K

Publishing Venue

Motorola

Related People

Robert H. Reuss: AUTHOR

Abstract

A modification to a CMOS-based BiCMOS proc- ess is described. With a modest increase in process complexity, a higher performance bipolar device mod- ule can be retrofitted into the baseline without per- turbation of the CMOS parameters. This allows an advanced NPN device to be incorporated into existing CMOS or BiCMOS designs to achieve improved per- formance without the need to shrink design rules. The bipolar module is placed aher the CMOS mod- ule because RTA is performed as the last high- temperature operation to maximize device perform- ance. Insertion of the bipolar module prior to the CMOS would result in dopant precipitation and poor electrical characteristics because furnace operations must be kept at c 900°C in advanced CMOS processes.

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MOTOROLA INC. Technical Developments Volume 20 October 1993

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REDUCED CAPACITANCE AND BASE-RESISTANCE NPN FOR CMOS-BASED BiCMOS

by Robert H. Reuss

  A modification to a CMOS-based BiCMOS proc- ess is described. With a modest increase in process complexity, a higher performance bipolar device mod- ule can be retrofitted into the baseline without per- turbation of the CMOS parameters. This allows an advanced NPN device to be incorporated into existing CMOS or BiCMOS designs to achieve improved per- formance without the need to shrink design rules. The bipolar module is placed aher the CMOS mod- ule because RTA is performed as the last high- temperature operation to maximize device perform- ance. Insertion of the bipolar module prior to the CMOS would result in dopant precipitation and poor electrical characteristics because furnace operations must be kept at c 900°C in advanced CMOS processes.

  The proposed method allows a Molly self-aligned, double polysilicon NPN structure as shown in Fig- ure 1 to be introduced into a production BiCMOS process to replace the lower performance transistor shown in Figure 2. The advantage of this approach is that significant improvement in bipolar device per- formance is achieved with only moderate increase in process complexity.

  Table 1 compares the individual operations in the bipolar module of the baseline BiCMOS proc- ess (with the standard, moderate-performance polysilicon emitter NPN) with a modified flow which

integrates the fully self-aligned, double-polysilicon device. The major differences between the two mod- ules are the extra steps required to form and isolate the p+ polysilicon base electrode ofthe double poly NPN. Eight additional process steps (highlighted in Table 1) are required, but no additional photo oper- ations or heat cycles are needed. There are three LPCVD depositions, one implant and two wet oxide etches, which all tend to be relatively inexpensive and non-critical, added to the baseline sequence. The two RIE's added to the baseline are more difficult and costly but are commonly performed in produc- tion. Overall the eight additional operations only a...