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Transceiverless Link Logic

IP.com Disclosure Number: IPCOM000007076D
Original Publication Date: 2002-Feb-22
Included in the Prior Art Database: 2002-Feb-22
Document File: 6 page(s) / 187K

Publishing Venue

Motorola

Related People

Edward J. Yurchik: AUTHOR [+4]

Abstract

The Transceiverless Link Logic circuit allows two micro-controllers to use USB for an Inter-processor Communication Link (ICL) without using conventional USB transceivers.

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Transceiverless Link Logic

Edward J. Yurchik, Carl Wojewoda, William Gabehart, and Mark Granger

Abstract

The Transceiverless Link Logic circuit allows two micro-controllers to use USB for an Inter-processor Communication Link (ICL) without using conventional USB transceivers.

Body

Two micro-controllers that use USB for an Inter-processor Communication Link (ICL) might be connected using conventional external USB transceivers as shown in Figure – 1.

Figure - 1

D+ and D- are differentially driven lines that are specified under USB requirements.  In common usage, D+ and D- are 10’s of cm or longer and can be up to 400 pF.  However, the requirements for an ICL are different.  The transmission length is perhaps at most 10 cm and a maximum of 20 pF.  So, the line conditioning that USB transceivers provide, and the noise immunity of a differential pair should not be required.  Therefore, the burden to provide a 4.0 V supply for the transceiver, as well as the transceivers to drive substantial capacitive loads may be avoided.

As far as micro-controllers A and B are concerned, as long as their respective TEXB, DIN, SE0, RCV, VP and VM signals behave as expected, the intervening circuit is unimportant.  So, consider the following block diagram in Figure-2.

Figure - 2

Now, D+ and D- are logic levels at some common voltage.  Again, as long as the behavior at each micro-controller is unchanged, the micro-controller is unaware that any change has been made.

The USB Transceiverless Link Logic can be described in the following behavior: (Refer to figure-3.)

Figure – 3

The signals RCV_A, RCV_B, VP_A and VM_A are equal to the state of D+_TLL.  The signals VM_A and VM_B are equal to the state of D-_TLL. 

If the control signal PASS is active, (logic level high)  then the following occurs:  The signal TXEN#_B will equal RCV_A, SEO_B will equal VP_A, DIN_B will equal VM_A, RCV_B will equal TXEN_A, VP_B will equal SE0_A and VM_B will equal DIN_A.  However, if PASS is logic level low, then the circuit will function as follows:

If SUSPEND is active, (logic level high) or if both sides of the TLL are not driving, (TXEN#_A and TXEN#_B are not equal to logic level zero), then the signal D+_TLL is equal to the logic level of SPEED and D-_TLL is equal to the inverse of the logic level of SPEED.

If the MODE setting signal is equal to a logic level zero while the signal TXEN#_A is active, (logic level zero) and the signal SEO_A is active, (logic level high) or the signal TXEN#_B is active (logic level zero) and the signal SEO_B is active, (logic level high) then both of the signals D+_TLL and D-_TLL are equal to a logic level zero....