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Integrated Level Shifters With Gating And Inhibiting

IP.com Disclosure Number: IPCOM000007078D
Original Publication Date: 2002-Feb-22
Included in the Prior Art Database: 2002-Feb-22
Document File: 2 page(s) / 69K

Publishing Venue

Motorola

Related People

Edward J. Yurchik: AUTHOR [+2]

Abstract

In many dual processor systems, the I/0 voltage levels between the two processors are different. Also, one device is often used as a peripheral and may be completely powered off while the other is still powered. External circuitry is then used to provide the following: 1) Voltage level shifting. 2) Gating (forcing a low logic level from an output buffer of the powered device) in order to prevent current leakage. 3) Inhibiting (forcing an inactive state to an input buffer of the powered device) in order to prevent false logic conditions. The external circuitry increases the cost and the size of the design. Circuitry is provided internally to overcome these disadvantages of prior systems.

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Integrated Level Shifters With Gating and Inhibiting

Edward J. Yurchik, and Carl Wojewoda

Abstract

In many dual processor systems, the I/0 voltage levels between the two processors are different.  Also, one device is often used as a peripheral and may be completely powered off while the other is still powered.    External circuitry is then used to provide the following: 1) Voltage level shifting.  2) Gating (forcing a low logic level from an output buffer of the powered device) in order to prevent current leakage.  3) Inhibiting (forcing an inactive state to an input buffer of the powered device) in order to prevent false logic conditions. The external circuitry increases the cost and the size of the design.  Circuitry is provided internally to overcome these disadvantages of prior systems.

Body

As shown in Figure-1, processor - B integrates level shifters as well as gating and inhibiting logic for both inputs and outputs.  The I/O voltage rail on processor - A is used on processor - B to control the voltage threshold on the interfacing signals.  When processor A is powered down, the gating logic will force a low logic level to the output buffer on processor B.  If a high logic level is driven by the output buffer on processor B, current will be wasted by forward biasing the ESD protection diode on the input buffer on processor A.  Forcing a low logic level prevents this current leakage.  Also, when processor A is powered down, inhibiting logic will force the appropriate state on the in...