Browse Prior Art Database

LOW POWER STEP EFFICIENCY IMPROVEMENT CIRCUITS

IP.com Disclosure Number: IPCOM000007083D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-25
Document File: 3 page(s) / 141K

Publishing Venue

Motorola

Related People

Rashid Osmani: AUTHOR [+2]

Abstract

Power amplifiers that are capable ofdelivering a range of power outputs are normally designed to operate most efficiently at the highest power level. This is because the current drain penalty for lower efficiency is worse at higher power output. When the same amplifier is used at a much reduced power level, it's efficiency is drastically reduced. If opera- tion at lower power output is a significant percent of total use, better efficiency at lower power levels will greatly improve performance. This paper describes two techniques to improve efhciency at low power levels while maintaining performance at the higher power levels.

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MOTOROLA Technical Developments Volumti 21 February 1994

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LOW POWER STEP EFFICIENCY IMPROVEMENT CIRCUITS

by Rashid Osmani and Dale Schwent

ABSTRACT

BIAS SWITCHING i,

  Power amplifiers that are capable ofdelivering a range of power outputs are normally designed to operate most efficiently at the highest power level. This is because the current drain penalty for lower efficiency is worse at higher power output. When the same amplifier is used at a much reduced power level, it's efficiency is drastically reduced. If opera- tion at lower power output is a significant percent of total use, better efficiency at lower power levels will greatly improve performance. This paper describes two techniques to improve efhciency at low power levels while maintaining performance at the higher power levels.

  The first technique to improve low power step efficiency is to switch the quiescent current of the PA in response to radio power step change. Figure 1 shows one possible implementation. At the lowest power steps, the PA linal;,device shown in the figure is essentially in class A mode ofoperation. By chang- ing the bias conditions 'at the lower steps, the PA could be kept in the class AB mode with the corresponding improvement in efficiency. In Figure 1, a D/A convertor controlled by the radio micropro- cessor is shown that can provide optimum bias to the tinal RF device of the power amplifier on every power step for maximum;, current drain improvement at every power step. The diode and resistor are part of the bias network while the inductors shown in Figure 1 provide isolation.

BACKGROUND

  Present day cellular systems in the United States and several other countries are based on analog stand- ards that have been in existence for at least the past ten years. New digital standards have been adopted by the cellular industry to increase the capacity of present cellular systems. In the United States, the new digital standards are for dual mode operation: The old AMPS and the new TDMA modes. In addi- tion to requirements of linearity in digital mode of operation, these new standards call for a larger range of power levels that subscriber units may have to use, to communicate with base stations. Old analog cellular standards call for seven 4-dB steps in power output ofthe radio transmitter. In the IS-54 speciti- cation for dual mode TDMA cellular radiotelephones, a provision is made for class IV portables. These portables operate at the same maximum power out- put as a conventional portable, but the minimum power output is 12 dB lower. It is expected that such a portable would be used at the lowest power steps in a microcell environment. On these lower power steps, existing portables have very poor transmitter efftciency due to the biasing and loading require- ments for maintaining linearity at higher power steps.

LOAD SWITCHING

  The second technique to improve low power step efficiency is to switch t:he load impedance at the output of the PA in respons...