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A FLEXIBLE SIZE 3-WIRE SERIAL EEPROM INTERFACE

IP.com Disclosure Number: IPCOM000007086D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-25
Document File: 4 page(s) / 189K

Publishing Venue

Motorola

Related People

Barry Moss: AUTHOR

Abstract

A serial EEPROM is an inexpensive and space efficient means of providing non-volatile storage for system configuration parameters. Unfortunately, the byte-oriented serial interfaces available on most sin- gle chip microcontrollers are not well suited to the 3-wire interface used on many popular serial EEPROMs. Consequently, the system software in products using serial EEPROMs is oflen required to directly toggle the chip enable, clock and data lines of the EEPROM interface, using a timer peripheral to time the bit periods. Serial EEPROMs ofien have slow access times and even slower program times, so a microprocessor can be required to waste signif- icant time during EEPROM accesses. However, with most new communications systems now incorpo- rating glue logic and some peripheral functions into an ASIC, a serial EEPROM hardware interface, such as the one described in this article, can be added to the ASIC at a minimal cost, allowing the micro- processor access to an external serial EEPROM as easily as most other microprocessor peripherals.

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0 M

MOIdROLA Technical Developments Volume 21 February 1994

A FLEXIBLE SIZE 3-WIRE SERIAL EEPROM INTERFACE

by Barry Moss

  A serial EEPROM is an inexpensive and space efficient means of providing non-volatile storage for system configuration parameters. Unfortunately, the byte-oriented serial interfaces available on most sin- gle chip microcontrollers are not well suited to the 3-wire interface used on many popular serial EEPROMs. Consequently, the system software in products using serial EEPROMs is oflen required to directly toggle the chip enable, clock and data lines of the EEPROM interface, using a timer peripheral to time the bit periods. Serial EEPROMs ofien have slow access times and even slower program times, so a microprocessor can be required to waste signif- icant time during EEPROM accesses. However, with most new communications systems now incorpo- rating glue logic and some peripheral functions into an ASIC, a serial EEPROM hardware interface, such as the one described in this article, can be added to

the ASIC at a minimal cost, allowing the micro- processor access to an external serial EEPROM as easily as most other microprocessor peripherals.

  The Flexible Size EEPROM Interface requires 6 memory locations (assuming an g-bit wide proces- sor data bus): a control register, address register and four data registers. The control register, EECR, is used to specify the size (32, 64, 128, or 256 words) and organization (8 bit or 16 bit) of the device, and the instruction to be executed (see Table 1). The address or instruction op-code (as required by the type of EEPROM instruction) is written to the address register, EADD. There are two incoming data shift registers, EEDATH and EEDATL, and two outgo-

ing data registers, EEDRH and EEDRL, to allow for both 8 and 16-bit wide EEPROM organizations.

El, EO El and EO define the type EEPROM access cycle, as shown In Table 3.

SIZE[l:O] EEPROM Size: Determines the size 01 the EEPROM used. Table 2 shows the EEPROM word size and the address bils to use for each size. OPCODEs from Table 1 must be placed In the

EEADD register as indicated In Table 2.

OR0 EEPROM Organization: 1 = 16 bits. 0 = 6 bits (defaull).

0 Motorola. 1°C. 1994 23

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MOTOROLA Technical Developments Volume 21 February 1994

Table 1 EEPROM Instruction Set

Program all addresses

Table 2 EEPROM Size Options

SIZE[l :O]

00

Words

32

Address Bits OPCODE Bits...