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Method for a consecutive events predictor for future low-power techniques in very high performance microprocessors

IP.com Disclosure Number: IPCOM000007094D
Publication Date: 2002-Feb-25
Document File: 7 page(s) / 54K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a consecutive event period predictor for low-power techniques in very high performance microprocessors. Benefits include improved system performance and improved power utilization.

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Method for a consecutive events predictor for future low-power techniques in very high performance microprocessors

Disclosed is a method for a consecutive event period predictor for low-power techniques in very high performance microprocessors. Benefits include improved system performance and improved power utilization.

Background

              High power consumption and the complexity of power management have become a major design constraint for very high frequency microprocessors. Due to very short cycle time in multi-GHz processors, many power reduction techniques may require multiple cycles to complete their tasks and obtain reasonable power reduction benefits, for example:

•             Logic-block disabling controls such as sleep transistors

•             Dynamic voltage scaling such as a multiple Vcc switching logic that increases or decreases power supply

•             Multi-cycle clock gating

•             Access controls due to cache misses and mis-predictions

              To achieve effective power reduction solutions, most of the techniques may require future information on multi-cycle activity events. During the execution of programs, periodical logic blocks in a processor can be enabled or disabled for multiple cycles. Enabled logic blocks may produce useless results consecutively consuming unnecessary power. These events are called consecutive activity events.

General description

              The disclosed method provides a mechanism for predicting multi-cycle periods of consecutive activity events. The method has the potential to be used for various multi-cycle power reduction techniques to relax the power constraints in multi-gigahertz high performance microprocessors.

              To illustrate the performance of the disclosed predictor, a consecutive cache miss events as a case study is conducted. Unified level-2 (L2) cache and the branch target buffer (BTB) are used for the study. For each structure, a specific design of the proposed prediction mechanism is associated to predict periods of consecutive cache miss events. The results show that on weighted averages of benchmarks about 70 to 90% prediction accuracy are observed and approximately 25% to 70% of predicted consecutive incorrect accesses are eliminated. In terms of instructions-per-clock (IPC) degradation due to incorrect predictions, no significant impact on overall performance is observed.

 


Advantages

              The disclosed method provides benefits over the conventional solution, including:

•             Improved system performance through improved prediction of consecutive events

•             Improved power utilization through the increased use of a lower-voltage state 

Detailed description

      The disclosed method includes a Current Event Predictor that is comprised of three major blocks (see Figure 1): the Current Consecutive Event Counter, the Next Consecutive Event Predictor, and the Consecutive Event Period Prediction Logic.   

      The Current Consecutive Event Counter keeps track of each occurrence of consecutive activity events. Output events of accesses such as cache hits or misses can be inputs t...