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NOVELL METHODOLOGY FOR OPERATING AN IXF32003 EVALUATION BOARD AS A VALID SONET OC-192/SDH STM-64 FRAME GENERATOR

IP.com Disclosure Number: IPCOM000007097D
Publication Date: 2002-Feb-26
Document File: 6 page(s) / 121K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to convert the evaluation system for an IXF32003 ASIC (more widely known as SLT100) to an SDH STM-64/SONET OC-192 frame generator. Apart from low cost, benefits include improved functionality (testing and demonstration).

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NOVELL METHODOLOGY FOR OPERATING AN IXF32003 EVALUATION BOARD AS A VALID SONET OC-192/SDH STM-64 FRAME GENERATOR

Disclosed is a method to convert the evaluation system for an IXF32003 ASIC (more widely known as SLT100) to an SDH STM-64/SONET OC-192 frame generator. Apart from low cost, benefits include improved functionality (testing and demonstration).

Background

              SLT is standard SDH/SONET network terminology for Section and Line Termination. The number 100 indicates a 10 Gbps rate.

General description

              The disclosed method enables the development of an SDH STM-64/SONET OC-192 frame generator by adapting an ASIC’s (IXF32003) evaluation board. Components of the disclosed method include:

•             Evaluation board

-         GD70002 motherboard

-         GD70001 (AT91F40416) controller daughterboard

-         Two (or one) GD70584/585 high-speed (HS) serializer/deserializer daughterboards

•             Standard RF coaxial cables with SMA connectors

•             Firmware (FW)

              Error monitoring and overhead handling are integral characteristics of the frame generator. The ASIC offers full error statistics (B1/B2) at the receiver. The user can acquire a good overview of the quality exhibited by the returning SDH/SONET signal, which is looped back by the target device, system, or network. Additionally, the ASIC has the capability to modify the SDH/SONET signal overhead portion either by itself or via an interface with an accordingly configured FPGA. Relying on this capability, a dedicated testing protocol could be built: Before frame transmission, one or more overhead bytes can be modified. Then the output frame will propagate in the target device or system or network. Finally the receiver can check, if the returning frames contain the expected overhead values.

Advantages

              The disclosed method improves the functionality of the IXF32003’s evaluation system to include frame generation for testing and demonstration purposes. This solution provides a relatively low-cost alternative to a higher-cost network analyzer.

Detailed description

              The disclosed method includes a set of printed circuit boards and firmware (see Figure 1). The motherboard (GD70002) is literarily built around the IXF32003 ASIC. A daughterboard (GD70001), which accommodates a micro controller (AT91F40416), is attached to the motherboard. The ASIC can be accessed and controlled by means of this daughterboard. Additionally, communication to a supervising host (e.g. laptop PC) can be established. Via this communication channel, the user can conveniently operate the system using the associated GUI.

              The interface to target device or system or network is implemented by a pair of identical daughterboards (GD70584/585) - one on line side and one on system side. Each function as both a high-speed serializer and deserializer. However, each could possibly be replaced by another MSA300-connector-compliant ser/des, such as one with optoelectronic conversion. In such a case, motherboard modification may be required. An optical module would be valuable on th...