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Method for exiting a processor power state based on a system timer interrupt

IP.com Disclosure Number: IPCOM000007116D
Publication Date: 2002-Feb-26
Document File: 3 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for exiting a processor power state based on a system timer interrupt. Benefits include improved operation of the system timer with ACPI power management C-states in a system utilizing an APIC.

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Method for exiting a processor power state based on a system timer interrupt 

Disclosed is a method for exiting a processor power state based on a system timer interrupt. Benefits include improved operation of the system timer with ACPI power management C-states in a system utilizing an APIC.

Background

              The conventional method of exiting a processor power state is to use the status of the Real-Time Clock (RTC) interrupt as a trigger even after the interrupt has been delivered to the processor by the Interrupt Controller (APIC). Attempts to utilize the processor power-saving states in conjunction with the APIC resulted in time loss on the display’s clock (see Figure 1). The loss is not acceptable for high-speed processors and future applications.

Description

              The disclosed method is a simple solution for a conflict between the APIC interrupt delivery mechanism and the use of processor power-saving states by PC operating systems. The RTC Interrupt status is directly presented to the power management logic for indicating the need for a break event (see Figure 2).

              The timing diagram (see Figure 3) illustrates how the problem is solved by the disclosed method. Conventionally, Interrupt controller status bits have been used to indicate to the power management logic when to break the CPU out of a low-power state to service an interrupt. However, with the APIC, edge-triggered interrupts (for example, the system timer) are delivered to the Local APIC but not processed by the I/O APIC....