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SERIALIZING HIERARCHICAL FORMATTING TOOL (SHiFT) FOR SERIALIZING PARALLEL TEST PATTERNS IN A PARTITIONED CHIP ARCHITECTURE

IP.com Disclosure Number: IPCOM000007130D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-27
Document File: 2 page(s) / 127K

Publishing Venue

Motorola

Related People

Steven E. Cozart: AUTHOR [+2]

Abstract

Partitioned chips present several problems related ,to testing. It is desirable to: 1) Provide a methodical flow from design to pat- tern formatting to simulation verification and final test patterns. Convert parallel test patterns (gener- ated by ATPG or any other method) to serialized vectors for testing the design, 2) Provide the ability to serialize ATPG gener- ated patterns for an embedded block in a chip. This would allow the block designer to verify that the vectors will be correctly serialized for their block. Furthermore, this feature could allow great flexibil- ity in partitioning ATPG in a complex chip by NOT requiring boundary scan elements.

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0 M MO-LA

Technical Developments Volume 21 February 1994

SERIALIZING HIERARCHICAL FORMATTING TOOL (SHim FOR SERIALIZING PARALLEL TEST PATTERNS IN A 6ARTITIONED

CHIP ARCHITECTURE

by Steven E. Cozart and Richard L. Greene

Partitioned chips present several problems related ,to testing. It is desirable to:

  1) Provide a methodical flow from design to pat- tern formatting to simulation verification and final test patterns. Convert parallel test patterns (gener- ated by ATPG or any other method) to serialized vectors for testing the design,

  2) Provide the ability to serialize ATPG gener- ated patterns for an embedded block in a chip. This would allow the block designer to verify that the vectors will be correctly serialized for their block. Furthermore, this feature could allow great flexibil- ity in partitioning ATPG in a complex chip by NOT requiring boundary scan elements.

  3) Provide a means to handle controllable, yet non-scanable signals (e.g. registers that can be loaded via a Serial Control Port).

SHiFT TEST METHODOLOGY FLOW:

SHiFT is composed of two pre-processing pro-

grams, a pattern formatting software library, and a proposed methodology that utilizes a suite of test development tools in addition to a synthesis tool for generating truth tables for the output pins of the blocks.

  An intermediate signal mapping file must be gen- erated for each block that defines all the scan signal names (both D and Q pins for each scan flop), in addition to pins and other non-scan signals.

  The map tile contains all the pertinent informa- tion from the design that is needed to perform pat- tern formatting. This file can be automatically gen- erated using a scan chain extraction tool in combination with the first SHiFT program. The sec- ond SHiPT program converts the mapfile to an inter- nal SHiFT signal definition tile. This C source code tile defines all the block's signals according to their specified classes. The second SHiFT program has the option of generating:code for the block level for simulation verification of for a hierarchical level.

For the hierarchical case, decoded outputs from each block must be described by truth tables. In the

OUT

above schematic, the signal OUT could become an truth table ofthe signal OUT is needed so that SHiFI input to some other block, and since OUT is not on can determine how to set OUT to a LOW or HIGH the scan chain directly, the other block would really for another blocks test. ~ Thus, these tables provide need to force signals A, B and C to get a value onto the capability to force the appropriate signals when OUT. another blocks ATPG vector needs to force an inter- mediate signal to a specific state.

OUT is classified as a decode signal; A, B, and C are considered the source signals of OUT. The There exists a very real possibility that two or

78 0 Motorola, 0°C. 1994

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