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Method for forming a package with high thermal conductivity that enables heat extraction from the front and back of an IC chip

IP.com Disclosure Number: IPCOM000007140D
Publication Date: 2002-Feb-27
Document File: 5 page(s) / 27K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for forming a package with high thermal conductivity that enables heat extraction from the front and back of an IC chip. Benefits include improved thermal performance.

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Method for forming a package with high thermal conductivity that enables heat extraction from the front and back of an IC chip

Disclosed is a method for forming a package with high thermal conductivity that enables heat extraction from the front and back of an IC chip. Benefits include improved thermal performance.

Background

              The disclosed method addresses the problem of thermal performance of processor packages. Conventional approaches extract the heat from the backside (only) of the IC chip. Consequently, a critical burden is placed on the performance of the thermal interface material (TIM) layer. The requirement is less than 0.15° C/W.

              The TIM thermal resistance target is approaching material capability limits and is already requiring expensive new material formulations and development of complex assembly approaches.

              Conventional air-cooled thermal solutions are fast approaching technology limits, necessitating migration to a more expensive liquid cooling option.

              In the conventional approach, heat is extracted primarily from the back of the die. This puts a heavy burden on the thermal performance of the interface layer connecting the back of the die to the package, including:

•             Ultra-high thermal performance TIM layer and an integrated heat spreader (IHS) are used to lower the thermal resistance and spread the heat efficiently.

•             Complex material formulations are required for meeting these thermal performance targets. These are expensive, have limited extendibility and the assembly integration and reliability are also of concern.

•             Arduous assembly process control is required to ensure minimum die warpage at the bonding temperature to carefully control the TIM thickness.

              These approaches are expensive and are reaching material and assembly process limits. Therefore, these approaches could not be extended for too long. The alternative to the conventional approach is liquid cooling, which is still expensive.

General description

      The disclosed method is a structure and method that significantly improves heat extraction from an IC chip. Heat is extracted both from the front and back of the die. The key elements of the method include:

•             The conventional Silica-filled underfill polymer layer is replaced by a material with high thermal conductivity. A polymer material is loaded with highly conductive fillers, such as BeO and Zr2O3. The highly conductive underfill layer improves the extraction of heat.

•             A large number of VCC, VSS, and thermal vias transfer the heat away from the IC surface and to the solid VCC, VSS Cu planes present in the substrate.

•             Solid Cu planes in the substrate spread the heat on a larger area.

•             Cu thickness in the VSS and VCC planes is increased to provide an increased thermal mass.

•             Alternatively, the substrate core can be configured from metal, such as Cu and Alloy-42, and can provide significant enhancement to the heat spreading efficiency.

Advantages

              The disclosed method provides several advantages, including:

•             High...