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Method for increasing interfacial crack resistance at the die/TIM interface by dimpling the die backside with laser milling

IP.com Disclosure Number: IPCOM000007149D
Publication Date: 2002-Feb-27
Document File: 3 page(s) / 368K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for increasing interfacial crack resistance at the die/TIM interface by dimpling the die backside with laser milling. Benefits include improved thermal performance and improved reliability.

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Method for increasing interfacial crack resistance at the die/TIM interface by dimpling the die backside with laser milling

Disclosed is a method for increasing interfacial crack resistance at the die/TIM interface by dimpling the die backside with laser milling. Benefits include improved thermal performance and improved reliability.

Background

              Die-attach delamination in stacked CSP packages and VF-BGAs is a chronic problem that limits the moisture sensitivity level at which the packages can be used (see Figure 1). With the requirement for higher solder reflow temperatures for lead-free solder applications, the delamination problem is becoming more acute. Delamination occurs because of poor adhesion strength between the die backside and the organic die-attach materials. No conventional solution to this problem exists. Different die attach materials are being evaluated and moisture-level ratings are being downgraded. The severity of the problem for lead-free application is beginning to be assessed with no potential solution paths identified.

              Delamination or interfacial cracking between solder TIM and die backside during reliability stresses results in an increase in the thermal resistance (see Figure 2). Cracks that initiate at the die corners and edges propagate rapidly along the smooth BSM/solder interface. Crack resistance increases as a crack progresses along the interface (a greater than 5X increase in crack resistance when the crack hits the disruption). No conventional solution exists for this problem for large die solder TIM applications. Evaluations of different solder materials and process optimizations are options being evaluated.

 Description

              The disclosed method includes a die backside surface dimpled by a...