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METHOD FOR SAVING BATTERY IN DECT ACTIVE UNLOCKED OR IDLE LOCKED STATES

IP.com Disclosure Number: IPCOM000007152D
Original Publication Date: 1994-Feb-01
Included in the Prior Art Database: 2002-Feb-28
Document File: 2 page(s) / 105K

Publishing Venue

Motorola

Related People

William F. Pickert: AUTHOR [+2]

Abstract

In a DECT system, one of the tasks of the porta- ble part (PP) while in the active unlocked or idle locked state is to build a channel list for synchro- nizing to or hand-off to the strongest radio fixed part (RFP). The PP performs this function by search- ing all the channels and slots in the DECT tiequency band for a DECT sync channel. Depending on the PP architecture, the process of searching the DECT frequency band adds to the overall power budget of the PI! This paper describes a method for reducing the power consumption of searching the DECT he- quency band.

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MOTOlROLA Technical Developments Volume 2l February 1994

METHOD FOR SAVING BATTERY IN DECT~ACTIVE UNLOCKED OR IDLE LOCKED STATES

by William F. Pickert and Charles John Malek~

  In a DECT system, one of the tasks of the porta- ble part (PP) while in the active unlocked or idle locked state is to build a channel list for synchro- nizing to or hand-off to the strongest radio fixed part (RFP). The PP performs this function by search- ing all the channels and slots in the DECT tiequency band for a DECT sync channel. Depending on the PP architecture, the process of searching the DECT frequency band adds to the overall power budget of the PI! This paper describes a method for reducing the power consumption of searching the DECT he- quency band.

  While searching for an RFP or a better RFP the PP may search channe1.s and slots where there are no RFPs transmitting. The PP will decode noise on these channel and slots. In the presence ofnoise (no signal), the synchronization channel falses on the average of once every 56.7 ms at the DECT bit rate of 1.152 Mbits/s. If one bit error is allowed in the synchronization word, the falsing rate increases to once every 3.4 ms.

  A typical hardware architecture for a DECT PP has dedicated hardware performing all of the physi- cal layer functions, including sync channel detec- tion, and a microprocessor system which has a low power operating mode for performing all the higher layer functions. Typically, the microprocessor system stays in the low power mode until the hardware

detects the DECT sync channel. Every time the syn- chronization channel falses, the microprocessor sys- tem must leave the low power consumption mode and evaluate the data even though the data is bad. The average power consumption ofthe microproces- sor system increases due to the falsing of the hard-

ware sync channel detector.

  An improved method would be to wake the microprocessor system only when there is good data to be evaluated. The high DECT bit rate (1.152 Mbits/s) makes it difftcult for a low power consum- i...