Browse Prior Art Database

MULTIPLEXER TEST STRUCTURE

IP.com Disclosure Number: IPCOM000007172D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-01
Document File: 2 page(s) / 95K

Publishing Venue

Motorola

Related People

Jose A. Lyon: AUTHOR [+3]

Abstract

This invention provides scan test capability for a multiplexer used in a dynamically sized bus.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 2

0 M MO-LA

Technical Developments Volume 22 June 1994

MULTIPLEXER TEST STRUCTURE

by Jose A. Lyon, Glenn Jackson and Randall Jones

FIELD OF THE INVENTION

DESCRIPTION OF THE INVENTION

This invention provides scan test capability for a multiplexer used in a dynamically sized bus.

BACKGROUND OF THE INVENTlON

  To test a dynamically sized bus, requires that logic be connected to the bus and be capable of configuring itself to transmit data in each of the different formats that the bus supports (i.e. 32 bit port size, 16 bit port size, and 8 bit port size). Since the design of a dynamically sized bus may be com- pleted prior to an actual module being connected to the bus, another problem arises: How does one test a bus that supports dynamic sizing if there is no logic connected to the bus? The problem also exists if a module is present but uses a smaller number of ports than the bus (i.e. a 16-bit port module on a 32-bit bus). In the past, this testing approach consisted of using scan chains, One ofthe scan chains would be used to control driving data into the mux, while the other would be used to capture the out- put of the multiplexer, This silicon overhead can be quite excessive if the dynamically sized multiplexer is tested with the use of scan chains.

  The invention consists of controlling the multiplexer input control, in addition to providing a continuity check of the pass gaies involved in dynam- ically sizing a bus. By verifying the continuity ofthe pass gates, stuck-at-l & stuck-at-0 faults can be detected without even running a bus cycle. The pass gates are connected as shown in Figure #I, with the input being driven by a register cell, and the output from the last pass gate being loaded into a register cell. To enable t...