Browse Prior Art Database

A MECHANISM TO OUTPUT INTERNAL STATE INFORMATION DURING IDLE BUS CYCLES

IP.com Disclosure Number: IPCOM000007175D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-01
Document File: 3 page(s) / 170K

Publishing Venue

Motorola

Related People

Joseph C. Circello: AUTHOR [+5]

Abstract

One of the most serious problems facing users of complex microprocessors (MPU) during system debug is the relative inability to determine what is happening within the device. As on-chip caches become larger and larger, the corresponding num- ber of external bus cycles needed to reference instruc- tions and operands is typically reduced. This factor coupled with the increased complexity caused by the implementation of sophisticated microarchitec- tures makes system-level debug and performance analysis difficult. The use of in-circuit emulators may provide relief to some users, but in many cases, the use of this technology may require the MPU to be configured in a manner that a failure completely disappears or real-time performance analysis is impossible.

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0 M MO-LA

Technical Developments Volume 22 June 1994

A MECHANISM TO OUTPUT INTERNAL STATE IFiFORMATION

DURING IDLE BUS CYCLES ;

by Joseph C. Circello, Richard H. Duerden, James G. Gay,

William B. Ledbetter, Jr. and Daniel M. McCarthy

  One of the most serious problems facing users of complex microprocessors (MPU) during system debug is the relative inability to determine what is happening within the device. As on-chip caches become larger and larger, the corresponding num- ber of external bus cycles needed to reference instruc- tions and operands is typically reduced. This factor coupled with the increased complexity caused by the implementation of sophisticated microarchitec- tures makes system-level debug and performance analysis difficult. The use of in-circuit emulators may provide relief to some users, but in many cases, the use of this technology may require the MPU to be configured in a manner that a failure completely disappears or real-time performance analysis is impossible.

  Previously, there have been a number of com- plex devices which provide visibility into the inter- nal state of the processor through special modes on operation. As examples, consider the OnCE (On-Chip Emulator) feature present in Motorola DSP56K products or the Background Debug Mode present in Motorola 683xx devices. These fimctions provide access to certain internal registers, but only through a special shift mode which operates at a slow speed.

The superscalar MC68060 microprocessor imple- ments a special debug visibility mode of operation

under control of a supervisor-mode programmable control bit. This mode operates in the following manner:

  If the control bit (accessible via the supervisor- mode MOVEC Instruction) is negated, then the part functions in a normal fashion with only the exter- nal memory requests driven onto the system bus.

This represents the default condition when the MPU is initialized.

  If the control bit is asserted, then the MC68060 drives internal state information onto the system bus during otherwise idle bus cycles.

  Specifically, the processor continually outputs internal state information if there are no pending internal bus requests and the system bus is granted to the MPU. In this mode of operation, the state information is output at full speed without any restric- tions concerning proc~essor configuration. The MC68060 outputs information defining the internal state of the processor's ~,instruction fetch and dual operand execution pipelines as well as compressed state information from the Bus Interface Controller (BIC).

  This approach works particularly well since the '060 (as well as most MPUs available today) falls into the processor classification labeled by David Patterson as an either/o< CPU:

Either the processo$s running at full speed -or- it is stalled waiting for a memory access

  On many pipelined microarchitectures, when the system bus is busy performing an external access, the internal pipeline(s) is typically stall...