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GUARDED GATED CHANNEL RESISTOR IN GaAs

IP.com Disclosure Number: IPCOM000007222D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-06
Document File: 2 page(s) / 129K

Publishing Venue

Motorola

Related People

Hua Fu: AUTHOR [+2]

Abstract

High values of resistance may be obtained by using a FET N+ (contact) implant in an ungated FET structure. The sheet rho for this process is con- trolled primarily by the implant dose and rapid ther- mal anneal temperature and shows excellent con- trol. The disadvantage is that a N+ resistor has low sheet resistivity and the construction ofa high value resistor requires considerable length (RaL/W). A high value resistor can also be made using bulk GaAs resistors with an N- (FET channel) implant (Figure la). However, due to the surface properties of GaAs, the exposed N- implant area is more sensitive to process induced surface depletion change and may easily exhibit *20% resistance variation. This sen- sitivity to process variation can be mitigated by a layout with several tloating gate Schottky (gate metal) strips across the resistor area (Figure lb). The gate metal blocks the N+ implant and protects the sen- sitive N- implant area surface from later process dam- age so that a high value resistor which is less sensi- tive to process variation can be obtained. Many gate strips are used to avoid a single large gate which would have a very low knee voltage and would tend to capacitively bypass the resistive channel at high frequency.

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M-LA Technical Developments Volume 22 June 1994

GUARDED GATED CHANNEL RESISTOR IN GaAs

by Hua Fu and George B. Norris

  High values of resistance may be obtained by using a FET N+ (contact) implant in an ungated FET structure. The sheet rho for this process is con- trolled primarily by the implant dose and rapid ther- mal anneal temperature and shows excellent con- trol. The disadvantage is that a N+ resistor has low sheet resistivity and the construction ofa high value resistor requires considerable length (RaL/W). A high value resistor can also be made using bulk GaAs resistors with an N- (FET channel) implant (Figure la). However, due to the surface properties of GaAs, the exposed N- implant area is more sensitive to process induced surface depletion change and may easily exhibit *20% resistance variation. This sen- sitivity to process variation can be mitigated by a layout with several tloating gate Schottky (gate metal) strips across the resistor area (Figure lb). The gate metal blocks the N+ implant and protects the sen- sitive N- implant area surface from later process dam- age so that a high value resistor which is less sensi- tive to process variation can be obtained. Many gate strips are used to avoid a single large gate which would have a very low knee voltage and would tend

to capacitively bypass the resistive channel at high frequency.

  Even with many gate strips, substrate depletion (backgating) on the gate stripe nearest the most pos- itive contact re...