Browse Prior Art Database

EXTERNAL MICRO-CODE FOR A MICROCODED DESIGN

IP.com Disclosure Number: IPCOM000007223D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-06
Document File: 2 page(s) / 100K

Publishing Venue

Motorola

Related People

Shvager Yenuda: AUTHOR [+3]

Abstract

The TPU is a Time Processing Unit, which is executing micro-instructions, by its micro-engine (RISC-like). These micro-instructions are stored in its internal ROM memory called micro-store. The internal micro-instruction and its address within the micro-store was unknown to the user/micro-code developer in the original design, the TPUl.

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0 M MO-LA

Technical Developments Volume 22 June 1994

EXTERNAL MICRO-CODE FOR A MICROCODED DESIGN

by Shvager Yenuda, Rosen Beni and Barak Hzhak

  The TPU is a Time Processing Unit, which is executing micro-instructions, by its micro-engine (RISC-like). These micro-instructions are stored in its internal ROM memory called micro-store. The internal micro-instruction and its address within the micro-store was unknown to the user/micro-code developer in the original design, the TPUl.

  In TPUl, there was a mechanism called "Emu- lation RAM:' to let the user develop and debug the microcode, instead of running the microcode from the micro-store ROM, the user had the possibility to write the microcode in an on chip RAM called "Emulation RAM:' and to let the TPUl run on that

  The "Emulation RAM" was used in TPUl for testing purpose also. During the production test, a test microcode was loaded into the "Emulation RAM" through the data bus of the chip, and then the TPU ran that microcode and the results were monitored on the TPU's external "TPU Channel pins." HAVING THE "Emulation RAM' ON-CHIP WAS A MUST IN ORDER TO TEST THE TPUl.

  This "MUST" was the reason for a major change in TPU2: The ability to test the TPU without the "MUST" to have an "Emulation RAM" on chip. Instead ofusing the "Emulation RAM" for microcode emulation, we used the multiplexing of the "TPU Channel Pins" to inject microcode through the pins, and also output the microcode address through the pins for test comprehency purpose.

Figure 0.1 TPUl testing

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Figure 0.2 T TPU2 testing

0 Motomla. 1°C. 1994 93

[This page contains 15 pictures or other non-text objects]

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Technical Developments Volume 22 June 1994

TESTING BY PIN MULTIPLEXING IN TPlJ2: instruction cycle in TPUl/TPU2 is 2 clock cycles long (4 ticks: Tl, T2, :T3,...