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A CMOS GATE CAPACITOR WITH ENHANCED PELIABILITY FOR OPTIMAL PERFORMANCE AND AREA UTILIZATION

IP.com Disclosure Number: IPCOM000007226D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-06
Document File: 3 page(s) / 138K

Publishing Venue

Motorola

Related People

James R. Lundberg: AUTHOR [+3]

Abstract

Power supply noise is a significant problem in large, synchronous, CMOS integrated circuits (e.g., microprocessors). First, noise affects the noise mar- gin of the circuits and, therefore, affects the fimc- tionally of the device (adversely impacting yields). Second, overall power-supply noise contracts and expands since VDD and VSS noise are generally sinusoidal but 180" out of phase with respect to each other. Simulations show that for each 1OOmV of power-supply collapse, there is approximately a 3% reduction in device speed. The frequency of supply noise is dictated by the package inductance and the overall chip capacitance (f = 1/(2rrsqrt(LC))), so it need not be in phase with the chip clocks and can affect any critical speed path. Power-supply collapse also adversely impacts yield and performance.

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Technical Developments Volume 22 June 1994

A CMOS GATE CAPACITOR WITH ENHANCED PELIABILITY FOR OPTIMAL PERFORMANCE AND AREA UTILIZATION

by James R. Lundberg, Jose T. Guzman and Stephen G. Jamison

  Power supply noise is a significant problem in large, synchronous, CMOS integrated circuits (e.g., microprocessors). First, noise affects the noise mar- gin of the circuits and, therefore, affects the fimc- tionally of the device (adversely impacting yields). Second, overall power-supply noise contracts and expands since VDD and VSS noise are generally sinusoidal but 180" out of phase with respect to each other. Simulations show that for each 1OOmV of power-supply collapse, there is approximately a 3% reduction in device speed. The frequency of supply noise is dictated by the package inductance and the overall chip capacitance (f = 1/(2rrsqrt(LC))), so it need not be in phase with the chip clocks and can affect any critical speed path. Power-supply collapse also adversely impacts yield and performance.

  To reduce cost, it is desirable to use smaller pack- ages (fewer pins) sacrificing power pins. This in turn exacerbates power supply noise due to an increase in the power-supply loop inductance. It is desirable to suppress power-supply noise, thus reducing pack- age cost to achieve a more competitive product.

  In the past, discrete external capacitors were used at the system level to suppress noise. However, as technology has scaled, the level of integration has increased and transition times have decreased exac- erbating supply noise. External capacitors have become ineffective due to the equivalent series induct- ance of the capacitor package and the integrated- circuit package.

  To address the above problems, designers have implemented on-die capacitors between VDD and VSS. High-performance microprocessors now routinely have on-die gate capacitancei,2,3. For an effective capacitor a gate capacitor is required (essen- tially a transistor with source and drain strapped together). Other dielectrics are too thick, requiring an inordinate amount ofarea. A gate capacitor (with source/drain) if biased in inversion, has a capact- tance per unit area gate of -0.345pF/cm2 at 1OOA

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Tox. The gate capacitor has virtually zero induct- ance and has an equivalent series resistance dictated by the aspect ratio of the device. The capacitor is fully compatible with standard CMOS processing. An NMOS device with gate connected to VDD and with both source and drain connected to VSS is one instantiation of a gate capacitor; another is a PMOS device with gate connected to VSS and with both source and drain connected to VDD.

  It is important to implement the gate capacitor with a high area-utilization efficiency since space on die i...