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Browse Prior Art Database

MULTI-LAYER CAPACITOR

IP.com Disclosure Number: IPCOM000007227D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-06
Document File: 1 page(s) / 47K

Publishing Venue

Motorola

Related People

Yeo-Hwan Yang: AUTHOR [+3]

Abstract

A novel approach to integrate MonoSolicon Capacitor (MSC) and Double Poly Capacitor (DPC) processes to achieve capacitance up to 3.1 ff/urn2 is proposed. Higher capacitance may be possible with thinner dielectric thickness.

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MOTOROLA Technical Developments Volume 22 June 1994

MULTI-LAYER CAPACITOR

by Yeo-Hwan Yang, Shu-Wu Chiu and Dan Lamey

MONOSILICON CAPACITOR:

  A novel approach to integrate MonoSolicon Capacitor (MSC) and Double Poly Capacitor (DPC) processes to achieve capacitance up to 3.1 ff/urn2 is proposed. Higher capacitance may be possible with thinner dielectric thickness.

  The current MOS6 BiCMOS 75% process offers MSC and DPC options. The MSC has high capaci- tance of 1.9 ff/um2, but with poor linearity of 1750 ppm/v. At same time, DPC offers low capacitance of 1.2 ff/um2 with excellent linearity of 90 ppm/v. Integrating the DPC on top of the MSC increases the capacitance up to 3.1 ff/um2. Desirable linearity can be obtained by ratio the area of MSC and DPC. See Figure 1 and 2. A brief description of the processes are in the following.

(1) Do the MSC implant (B+ll, 5E15, 40Kev) on the active area (N well).
(2) Do the dry oxidation (150A on test water).
(3) Put down the Poly 3200A
(4) Do the pocl doping on Poly

DOUBLE POLY CAPACITOR:

(1) Do dry oxidation (BOA on test wafer) on top of the MSC's Poly.
(2) Deposit nitride 150A on top ofoxide.
(3) Do dry oxidation (235A on test wafer) on top of nitride.
(4) Do ON0 RIE.
(5) Remove the oxide from top the nitride.
(6) Do final dry oxidation (15OA on test wafer) on top ofnitride.
(7) Deposit Poly 3500A.
(8) Do pocl doping on Poly

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