Browse Prior Art Database

Method for a BBUL package with two-sided heat removal Disclosure Number: IPCOM000007238D
Publication Date: 2002-Mar-06
Document File: 7 page(s) / 330K

Publishing Venue

The Prior Art Database


Disclosed is a method for a bumpless build-up layer (BBUL) package with two-sided heat removal. Benefits include improved thermal performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 35% of the total text.

Method for a BBUL package with two-sided heat removal

Disclosed is a method for a bumpless build-up layer (BBUL) package with two-sided heat removal. Benefits include improved thermal performance.


      BBUL technology is conventionally recognized for its cost, electrical (power delivery and high-speed I/O), mechanical, routing, and other advantages. However, thermally, it performs similarly to standard flip-chip packaging. Thermal issues are critical for future microprocessor products, and few cost-effective solutions are available.

      The conventional solution is to interface a standard thermal device with the exposed backside of the die (see Figure 1). Microelectronic die (1) is embedded in substrate core (2) using the encapsulation material (3). Build-up layers (4) are formed directly on top of the active surface of die (1). In this illustration, the socket (5) connects the BBUL package to the motherboard (6). In a standard power decoupling solution, large landside decoupling capacitors (7) are surface-mounted onto the BBUL package, covering most of the die shadow area (see Figure 2). Alternatively or in addition, die-side decoupling capacitors (see Figure 1, 8) can be embedded into substrate core (2). An integrated heat spreader (9) removes heat from the exposed backside of die (1) and is cooled by the heatsink (10).

General description

      The disclosed method includes a BBUL electronic package with heatsinks attached on both the backside and the frontside of the die.

      The key elements of the method include:

•             Combination of cost savings with the electrical, mechanical, and routing advantages of            BBUL packaging with the thermal advantage of two-sided heat removal

•             Improvement of 15% to 20% over the thermal performance of standard flip-chip                   packaging


      The disclosed method presents advantages, including:

•             Same advantages as conventional BBUL plus significantly enhanced thermal               performance

•             Junction-to-ambient thermal resistance can be as much as 15% to 20% lower than for the                  standard flip-chip packaging technology

Detailed description

      The disclosed method extends the BBUL packaging concept by a two-sided heat removal scheme that is enabled by the physical thinness of BBUL packages. Simulations demonstrate a 15% to 20% enhancement of thermal performance as compared to a standard flip-chip package with single-sided thermal solution.

              The low inductance of BBUL enables the strategic placement of landside decoupling capacitors (see Figure 3, 11). They have low capacitance, low parasitic inductance, and a small form factor. They can be placed near electrical hot spots while the larger capacitors (7) are relocated to the periphery of the die shadow (see Figure 4) or replaced by die-side capacitors (see Figure 3, 8). As a result, a partial depopulation of the backside of the BBUL package occurs and facilitates frontside heat removal. Power delivery cost savings due to reduced capacitor count may result.

              The build-up layers (4) are modifi...