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PREVENTING FALSE LATCHING IN VLSI CIRCUITS

IP.com Disclosure Number: IPCOM000007257D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2002-Mar-07
Document File: 4 page(s) / 132K

Publishing Venue

Motorola

Related People

Zahid Ahsanullah: AUTHOR [+2]

Abstract

A very common problem in modern VLSI cir- cuits is false latching due to glitches in the enable signal arising out of violation of the setup time. An Ideal enable signal has a setup and hold time rela- tive to the latching clock. Violations of this setup and hold time can result due to the following reasons: 1. An oversight in design which did not account for any number of boundary conditions which cause the enable signal timing requirements to be vio- lated. For instance loading due long metal lines.

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Technical Developments Volume 22 June 1994

PREVENTING FALSE LATCHING IN VLSI CIRCUITS

by Zahid Ahsanullah and Abbas Rashid

1.0 FALSE LATCHING PROBLEM

  A very common problem in modern VLSI cir- cuits is false latching due to glitches in the enable signal arising out of violation of the setup time. An Ideal enable signal has a setup and hold time rela- tive to the latching clock. Violations of this setup and hold time can result due to the following reasons:

1. An oversight in design which did not account for any number of boundary conditions which cause the enable signal timing requirements to be vio- lated. For instance loading due long metal lines.

2. A design that was tine tuned for a process win- dow which changed due to changes in process technology thus changing timings.

3. Timing side-effects resulting from design changes which are needed to fix bugs.

4.A noisy enable signal that can have unpredict- able glitches,

  In all these cases the timing violation needs to be fixed, but in many cases especially in a mature design, it is sometimes not practical to fix this viola- tion without major changes to the circuit.

  Our proposed latch is ideal for such a situation since it forgives violations of the setup times. It is also a good solution in cases where signals travel long distances and are known speed paths that need to be reliably latched.

  Figure la shows the conventional latch and Figure lb shows our proposed design, while Figure 2 com- pares the timing behavior of our latch (Figure 2a) as opposed to a conventional latch (Figure 2b).

F Motorola. 1°C. 1994 129

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MOTOROLA Technical Developments Volume 22 June 1994

Figure 1.

(a)

ENABLE

PHI

Figure 2

PHl

1 I 1 I

E!!ABLE

n-PUT

PHI

1 I I I 1

PHZ I I I I 1 EVABLE 1

I I


(b)

130 0 Motorola. I"C, 1994

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MOTOROLA Technical Developments Volume 22 June 1994

that the latch does not significantly affect output loading as the output sampling transistor is off at the time of latching. The extra loading to the 'ena- ble' due to the invertor has negligible effects on the circuit.

  A drawback ofthis circuit is the additional gates needed to implement it over the latch it is intended to rep...